IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 30

Volume 30, Number 1, January 2011

• Sachin S. Sapatnekar:
  Editorial. 1
  
• Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay:
  Floorplanning for Partially Reconfigurable FPGAs. 8-17
  
• Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu:
  Toward Automated ECOs in FPGAs. 18-30
  
• Osnat Keren, Ilya Levin, Radomir S. Stankovic:
  Determining the Number of Paths in Decision Diagrams by Using Autocorrelation Coefficients. 31-44
  
• Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif:
  Hierarchical Multialgorithm Parallel Circuit Simulation. 45-58
  
• Lin Xie, Azadeh Davoodi:
  Bound-Based Statistically-Critical Path Extraction Under Process Variations. 59-71
  
• Tai-Hsuan Wu, Azadeh Davoodi, Jeffrey T. Linderoth:
  GRIP: Global Routing via Integer Programming. 72-84
  
• Qiang Ma, Linfu Xiao, Yiu-Cheong Tam, Evangeline F. Y. Young:
  Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints. 85-95
  
• Hochang Jang, Deokjin Joo, Taewhan Kim:
  Buffer Sizing and Polarity Assignment in Clock Tree Synthesis for Power/Ground Noise Minimization. 96-109
  
• Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung:
  Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment. 110-123
  
• Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini:
  Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. 124-134
  
• Dong Xiang, Ye Zhang:
  Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme. 135-147
  
• Sounil Biswas, Ronald D. Blanton:
  Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data. 148-158
  
• Javid Jaffari, Mohab Anis:
  On Efficient LHS-Based Yield Analysis of Analog Circuits. 159-163
  

Volume 30, Number 2, February 2011

• Prashant Saxena, Yao-Wen Chang:
  Guest Editorial. 165-166
  
• Renshen Wang, Yulei Zhang, Nan-Chi Chou, Evangeline F. Y. Young, Chung-Kuan Cheng, Ronald L. Graham:
  Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications. 167-179
  
• Michael Eick, Martin Strasser, Kun Lu, Ulf Schlichtmann, Helmut E. Graeb:
  Comprehensive Generation of Hierarchical Placement Rules for Analog Integrated Circuits. 180-193
  
• Gaurav Ajwani, Chris Chu, Wai-Kei Mak:
  FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. 194-204
  
• Lijuan Luo, Tan Yan, Qiang Ma, Martin D. F. Wong, Toshiyuki Shibuya:
  A New Strategy for Simultaneous Escape Based on Boundary Routing. 205-214
  
• Tsung-Wei Huang, Tsung-Yi Ho:
  A Two-Stage Integer Linear Programming-Based Droplet Routing Algorithm for Pin-Constrained Digital Microfluidic Biochips. 215-228
  
• Yi-Wei Lin, Malgorzata Marek-Sadowska, Wojciech Maly:
  On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits. 229-241
  
• M. Haykel Ben Jamaa, Kartik Mohanram, Giovanni De Micheli:
  An Efficient Gate Library for Ambipolar CNTFET Logic. 242-255
  
• Vittorio Rizzoli, Diego Masotti, Franco Mastri, E. Montanari:
  System-Oriented Harmonic-Balance Algorithms for Circuit-Level Simulation. 256-269
  
• Min Gong, Hai Zhou, Li Li, Jun Tao, Xuan Zeng:
  Binning Optimization for Transparently-Latched Circuits. 270-283
  
• Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif:
  Simultaneous Layout Migration and Decomposition for Double Patterning Technology. 284-294
  
• Feng Wang, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan:
  Variation-Aware Task and Communication Mapping for MPSoC Architecture. 295-307
  
• Tracey Y. Zhou, Hang Liu, Dian Zhou, Tuna B. Tarim:
  A Fast Analog Circuit Analysis Algorithm for Design Modification and Verification. 308-313
  
• Guo Yu, Peng Li:
  Hierarchical Analog/Mixed-Signal Circuit Optimization Under Process Variations and Tuning. 313-317
  
• Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
  Power and Thermal Constrained Test Scheduling Under Deep Submicron Technologies. 317-322
  

Volume 30, Number 3, March 2011

• Mark Po-Hung Lin, Hongbo Zhang, Martin D. F. Wong, Yao-Wen Chang:
  Thermal-Driven Analog Placement Considering Device Matching. 325-336
  
• Masoud Rostami, Kartik Mohanram:
  Dual-V_th Independent-Gate FinFETs for Low Power Logic Circuits. 337-349
  
• Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida:
  A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. 350-363
  
• Sourajeet Roy, Anestis Dounavis:
  Transient Simulation of Distributed Networks Using Delay Extraction Based Numerical Convolution. 364-373
  
• Pekka Miettinen, Mikko Honkala, Janne Roos, Martti Valtonen:
  PartMOR: Partitioning-Based Realizable Model-Order Reduction Method for RLC Circuits. 374-387
  
• Lerong Cheng, Puneet Gupta, Costas J. Spanos, Kun Qian, Lei He:
  Physically Justifiable Die-Level Modeling of Spatial Variation in View of Systematic Across Wafer Variability. 388-401
  
• Chunyang Feng, Hai Zhou, Changhao Yan, Jun Tao, Xuan Zeng:
  Efficient Approximation Algorithms for Chemical Mechanical Polishing Dummy Fill. 402-415
  
• Yifang Liu, Rupesh S. Shelar, Jiang Hu:
  Simultaneous Technology Mapping and Placement for Delay Minimization. 416-426
  
• Ying-Cherng Lan, Yueh-Chi Lin, Shih-Hsin Lo, Yu Hen Hu, Sao-Jie Chen:
  A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel. 427-440
  
• Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
  Automatic Pipelining From Transactional Datapath Specifications. 441-454
  
• Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu:
  Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains. 455-463
  
• C.-C. Chen, C.-W. Kuo, Y.-J. Yang:
  Generating Passive Compact Models for Piezoelectric Devices. 464-467
  
• Young-Pyo Joo, Sungchan Kim, Soonhoi Ha:
  Fast Communication Architecture Exploration of Processor Pool-Based MPSoC via Static Performance Analysis. 468-472
  

Volume 30, Number 4, April 2011

• Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo Noguera, Kees A. Vissers, Zhiru Zhang:
  High-Level Synthesis for FPGAs: From Prototyping to Deployment. 473-491
  
• Luca Benini, Luca P. Carloni:
  Guest Editorial: Special Section on the ACM/IEEE Symposium on Networks-on-Chip 2010. 492-493
  
• Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin:
  A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. 494-507
  
• Paul Bogdan, Radu Marculescu:
  Non-Stationary Traffic Analysis and Its Implications on Multicore Platform Design. 508-519
  
• Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano:
  Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. 520-533
  
• Samuel Rodrigo, José Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato:
  Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems. 534-547
  
• Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh:
  Extending the Effective Throughput of NoCs With Distributed Shared-Buffer Routers. 548-561
  
• Zhuo Feng, Xueqian Zhao, Zhiyu Zeng:
  Robust Parallel Preconditioned Power Grid Simulation on GPU With Adaptive Runtime Performance Modeling and Optimization. 562-573
  
• Xiao-Chun Li, Jun-Fa Mao, Madhavan Swaminathan:
  Transient Analysis of CMOS-Gate-Driven RLGC Interconnects Based on FDTD. 574-583
  
• Jingtong Hu, Wei-Che Tseng, Chun Jason Xue, Qingfeng Zhuge, Yingchao Zhao, Edwin Hsing-Mean Sha:
  Write Activity Minimization for Nonvolatile Main Memory Via Scheduling and Recomputation. 584-592
  
• Ming-Chao Chiang, Tse-Chen Yeh, Guo-Fu Tseng:
  A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development. 593-606
  
• Jongeun Lee, Aviral Shrivastava:
  Static Analysis of Register File Vulnerability. 607-616
  
• Scott Little, David Walter, Chris J. Myers, Robert A. Thacker, Satish Batchu, Tomohiro Yoneda:
  Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets. 617-630
  
• Santino Mele, Michele Favalli:
  A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits. 631-635
  

Volume 30, Number 5, May 2011

• Ganghee Lee, Kiyoung Choi, Nikil D. Dutt:
  Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. 637-650
  
• Yu-Shen Yang, Subarna Sinha, Andreas G. Veneris, Robert K. Brayton:
  Automating Logic Transformations With Approximate SPFDs. 651-664
  
• Tejaswi Gowda, Sarma B. K. Vrudhula, Niranjan Kulkarni, Krzysztof S. Berezowski:
  Identification of Threshold Functions and Synthesis of Threshold Networks. 665-677
  
• Aijiao Cui, Chip-Hong Chang, Sofiène Tahar, Amr T. Abdel-Hamid:
  A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design. 678-690
  
• Nahi H. Abdul Ghani, Farid N. Najm:
  Fast Vectorless Power Grid Verification Under an RLC Model. 691-703
  
• Evanthia Papadopoulou:
  Net-Aware Critical Area Extraction for Opens in VLSI Circuits Via Higher-Order Voronoi Diagrams. 704-717
  
• Tao Huang, Liang Li, Evangeline F. Y. Young:
  On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees. 718-731
  
• Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung Kyu Lim:
  Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs. 732-745
  
• Huan Ren, Shantanu Dutt:
  Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous V_dd, V_th Assignments, Gate Sizing, and Placement. 746-759
  
• Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra:
  Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging. 760-773
  
• Maurizio Palesi, Giuseppe Ascia, Fabrizio Fazzino, Vincenzo Catania:
  Data Encoding Schemes in Networks on Chip. 774-786
  
• Xrysovalantis Kavousianos, Krishnendu Chakrabarty:
  Generation of Compact Stuck-At Test Sets Targeting Unmodeled Defects. 787-791
  

Volume 30, Number 6, June 2011

• Bo Liu, Francisco V. Fernández, Georges G. E. Gielen:
  Efficient and Accurate Statistical Analog Yield Optimization and Variation-Aware Circuit Sizing Based on Computational Intelligence Techniques. 793-805
  
• Dmitri Maslov, Mehdi Saeedi:
  Reversible Circuit Optimization Via Leaving the Boolean Domain. 806-816
  
• Cliff Chiung-Yu Lin, Yao-Wen Chang:
  Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips. 817-828
  
• Shahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh:
  SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs. 829-840
  
• Antonio J. García-Loureiro, Natalia Seoane, Manuel Aldegunde, Raúl Valín Ferreiro, Asen Asenov, A. Martinez, Karol Kalna:
  Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors. 841-851
  
• Vineeth Veetil, Kaviraj Chopra, David Blaauw, Dennis Sylvester:
  Fast Statistical Static Timing Analysis Using Smart Monte Carlo Techniques. 852-865
  
• Quan Chen, Wim Schoenmaker, Peter Meuris, Ngai Wong:
  An Effective Formulation of Coupled Electromagnetic-TCAD Simulation for Extremely High Frequency Onward. 866-876
  
• Anand Rajaram, David Z. Pan:
  Robust Chip-Level Clock Tree Synthesis. 877-890
  
• Nigel Drego, Anantha P. Chandrakasan, Duane S. Boning, Devavrat Shah:
  Reduction of Variation-Induced Energy Overhead in Multi-Core Processors. 891-904
  
• Kyungsu Kang, Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung:
  Runtime Power Management of 3-D Multi-Core Architectures Under Peak Power and Temperature Constraints. 905-918
  
• Mincent Lee, Li-Ming Denq, Cheng-Wen Wu:
  A Memory Built-In Self-Repair Scheme Based on Configurable Spares. 919-929
  
• Tong-Yu Hsieh, Kuen-Jong Lee, Melvin A. Breuer:
  An Error-Tolerance-Based Test Methodology to Support Product Grading for Yield Enhancement. 930-934
  
• Dani Tannir, Roni Khazaka:
  Adjoint Sensitivity Analysis of Nonlinear Distortion in Radio Frequency Circuits. 934-939
  
• Jason Cong, Hui Huang, Wei Jiang:
  Pattern-Mining for Behavioral Synthesis. 939-944
  

Volume 30, Number 7, July 2011

• Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose:
  Error Tolerance in Server Class Processors. 945-959
  
• Angelo Brambilla, Giambattista Gruosso, Giancarlo Storti Gajani:
  A Probe-Based Harmonic Balance Method to Simulate Coupled Oscillators. 960-971
  
• Onder Suvak, Alper Demir:
  On Phase Models for Oscillators. 972-985
  
• Yang Zhao, Tao Xu, Krishnendu Chakrabarty:
  Broadcast Electrode-Addressing and Scheduling Methods for Pin-Constrained Digital Microfluidic Biochips. 986-999
  
• Zigang Xiao, Evangeline F. Y. Young:
  Placement and Routing for Cross-Referencing Digital Microfluidic Biochips. 1000-1010
  
• Nikolay Rubanov:
  A General Framework to Perform the MAX/MIN Operations in Parameterized Statistical Timing Analysis Using Information Theoretic Concepts. 1011-1019
  
• Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak:
  SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. 1020-1033
  
• Jai-Ming Lin, Zhi-Xiong Hung:
  UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-Placed Modules. 1034-1044
  
• Sheng Chou, Cheng-Shen Han, Po-Kai Huang, Ko-Fan Tien, Tsung-Yi Ho:
  An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis. 1045-1057
  
• Yen-Tzu Lin, R. D. (Shawn) Blanton:
  METER: Measuring Test Effectiveness Regionally. 1058-1071
  
• Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
  BIST-Based Fault Diagnosis for Read-Only Memories. 1072-1085
  

Volume 30, Number 8, August 2011

• Husni M. Habal, Helmut Graeb:
  Constraint-Based Layout-Driven Sizing of Analog Circuits. 1089-1102
  
• Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra:
  Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations. 1103-1113
  
• Seungwhun Paik, Seonggwan Lee, Youngsoo Shin:
  Retiming Pulsed-Latch Circuits With Regulating Pulse Width. 1114-1127
  
• Wei Hu, Jason Oberg, Ali Irturk, Mohit Tiwari, Timothy Sherwood, Dejun Mu, Ryan Kastner:
  Theoretical Fundamentals of Gate Level Information Flow Tracking. 1128-1140
  
• Jorge Fernandez Villena, L. Miguel Silveira:
  Multi-Dimensional Automatic Sampling Schemes for Multi-Point Modeling Methodologies. 1141-1151
  
• Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou:
  MSV-Driven Floorplanning. 1152-1162
  
• Se Hun Kim, Saibal Mukhopadhyay, Wayne Wolf:
  Modeling and Analysis of Image Dependence and Its Implications for Energy Savings in Error Tolerant Image Processing. 1163-1172
  
• Ali Irturk, Janarbek Matai, Jason Oberg, Jeffrey Su, Ryan Kastner:
  Simulate and Eliminate: A Top-to-Bottom Design Methodology for Automatic Generation of Application Specific Architectures. 1173-1183
  
• Jer-Min Jou, Yun-Lung Lee, Sih-Sian Wu:
  Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis. 1184-1196
  
• Paul Bogdan, Radu Marculescu:
  Hitting Time Analysis for Fault-Tolerant Communication at Nanoscale in Future Multiprocessor Platforms. 1197-1210
  
• Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
  A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design. 1211-1224
  
• Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, P. Szczerbicki, Jerzy Tyszer:
  Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. 1225-1238
  
• Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
  Effective Robustness Analysis Using Bounded Model Checking Techniques. 1239-1252
  
• Irith Pomeranz:
  Generation of Multi-Cycle Broadside Tests. 1253-1257
  
• Ahmed Shebaita, Debasish Das, Dusan Petranovic, Yehea I. Ismail:
  A Novel Moment Based Framework for Accurate and Efficient Static Timing Analysis. 1258-1262
  

Volume 30, Number 9, September 2011

• Adam B. Kinsman, Nicola Nicolici:
  Automated Range and Precision Bit-Width Allocation for Iterative Computations. 1265-1278
  
• Weikang Qian, Marc D. Riedel, Hongchao Zhou, Jehoshua Bruck:
  Transforming Probabilities With Combinational Logic. 1279-1292
  
• Hitoshi Mizunuma, Yi-Chang Lu, Chia-Lin Yang:
  Thermal Modeling and Analysis for 3-D ICs With Integrated Microchannel Cooling. 1293-1306
  
• Chenjie Gu:
  QLMOR: A Projection-Based Nonlinear Model Order Reduction Approach Using Quadratic-Linear Representation of Nonlinear Systems. 1307-1320
  
• Cheng Zhuo, Kaviraj Chopra, Dennis Sylvester, David Blaauw:
  Process Variation and Temperature-Aware Full Chip Oxide Breakdown Reliability Analysis. 1321-1334
  
• Yen-Hung Lin, Shu-Hsin Chang, Yih-Lang Li:
  Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization. 1335-1348
  
• Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay:
  Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems. 1349-1358
  
• Raid Zuhair Ayoub, Krishnam Raju Indukuri, Tajana Simunic Rosing:
  Temperature Aware Dynamic Workload Scheduling in Multisocket CPU Servers. 1359-1372
  
• Jason Thong, Nicola Nicolici:
  An Optimal and Practical Approach to Single Constant Multiplication. 1373-1386
  
• Daniel Gebhardt, JunBok You, Kenneth S. Stevens:
  Design of an Energy-Efficient Asynchronous NoC and Its Optimization Tools for Heterogeneous SoCs. 1387-1399
  
• Ahcène Bounceur, Salvador Mir, Haralampos-G. D. Stratigopoulos:
  Estimation of Analog Parametric Test Metrics Using Copulas. 1400-1410
  
• Stephan Eggersglüß, Rolf Drechsler:
  Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. 1411-1415
  
• Irith Pomeranz:
  Scan Shift Power of Functional Broadside Tests. 1416-1420
  
• Erdem Serkan Erdogan, Sule Ozev:
  A Multi-Site Test Solution for Quadrature Modulation RF Transceivers. 1421-1425
  

Volume 30, Number 10, October 2011

• Vijay Janapa Reddi, David Brooks:
  Resilient Architectures via Collaborative Design: Maximizing Commodity Processor Performance in the Presence of Variations. 1429-1445
  
• Subhankar Mukherjee, Pallab Dasgupta, Siddhartha Mukhopadhyay:
  Auxiliary Specifications for Context-Sensitive Monitoring of AMS Assertions. 1446-1457
  
• Bo Liu, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen:
  Synthesis of Integrated Passive Components for High-Frequency RF ICs Based on Evolutionary Computation and Machine Learning Techniques. 1458-1468
  
• Xuanxing Xiong, Jia Wang:
  Dual Algorithms for Vectorless Power Grid Verification Under Linear Current Constraints. 1469-1482
  
• Harish S. Bhat, Braxton Osting:
  2-D Inductor-Capacitor Lattice Synthesis. 1483-1492
  
• Mohammad Ghasemazar, Massoud Pedram:
  Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing. 1493-1506
  
• Johnnie Chan, Gilbert Hendry, Keren Bergman, Luca P. Carloni:
  Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks. 1507-1520
  
• Wooyoung Jang, David Z. Pan:
  Application-Aware NoC Design for Efficient SDRAM Access. 1521-1533
  
• Kuen-Jong Lee, Wei-Cheng Lien, Tong-Yu Hsieh:
  Test Response Compaction via Output Bit Selection. 1534-1544
  
• Min Li, Michael S. Hsiao:
  3-D Parallel Fault Simulation With GPGPU. 1545-1555
  
• ShengYu Shen, Ying Qin, LiQuan Xiao, KeFei Wang, Jianmin Zhang, Sikun Li:
  A Halting Algorithm to Determine the Existence of the Decoder. 1556-1563
  
• Lin Yuan, Sean Leventhal, Junjun Gu, Gang Qu:
  TALk: A Temperature-Aware Leakage Minimization Technique for Real-Time Systems. 1564-1568
  
• Tongquan Wei, Xiaodao Chen, Shiyan Hu:
  Reliability-Driven Energy-Efficient Task Scheduling for Multiprocessor Real-Time Systems. 1569-1573
  
• Paolo Maffezzoni, Dario D'Amore:
  Analysis of Phase Diffusion Process in Oscillators Due to White and Colored-Noise Sources. 1574-1578
  
• Irith Pomeranz:
  Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults. 1579-1583
  

Volume 30, Number 11, 2011

• Younghyun Kim, Sangyoung Park, Youngjin Cho, Naehyuck Chang:
  System-Level Online Power Estimation Using an On-Chip Bus Performance Monitoring Unit. 1585-1598
  
• Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee W. Yoon, Doosan Cho, Yunheung Paek:
  High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures. 1599-1609
  
• Xueqian Zhao, Yonghe Guo, Xiaodao Chen, Zhuo Feng, Shiyan Hu:
  Hierarchical Cross-Entropy Optimization for Fast On-Chip Decap Budgeting. 1610-1620
  
• Duo Ding, J. Andres Torres, David Z. Pan:
  High Performance Lithography Hotspot Detection With Successively Refined Pattern Identifications and Machine Learning. 1621-1634
  
• Young-Joon Lee, Sung Kyu Lim:
  Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs. 1635-1648
  
• Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang:
  Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs. 1649-1662
  
• Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson, Gwan Choi:
  Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. 1663-1676
  
• Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha:
  Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. 1677-1690
  
• David Boland, George A. Constantinides:
  Bounding Variable Values and Round-Off Effects Using Handelman Representations. 1691-1704
  
• Brandon Noia, Krishnendu Chakrabarty, Sandeep Kumar Goel, Erik Jan Marinissen, Jouke Verbree:
  Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. 1705-1718
  
• Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi:
  A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects. 1719-1730
  
• Chih-Sheng Hou, Jin-Fu Li, Tsu-Wei Tseng:
  Memory Built-in Self-Repair Planning Framework for RAMs in SoCs. 1731-1743
  
• Ozgur Sinanoglu, Sobeeh Almukhaizim:
  Unified 2-D X-Alignment for Improving the Observability of Response Compactors. 1744-1757
  
• Eric A. Foreman, Peter A. Habitz, Ming-C. Cheng, Christino Tamon:
  Inclusion of Chemical-Mechanical Polishing Variation in Statistical Static Timing Analysis. 1758-1762
  
• Zhen Chen, Krishnendu Chakrabarty, Dong Xiang:
  MVP: Minimum-Violations Partitioning for Reducing Capture Power in At-Speed Delay-Fault Testing. 1762-1767
  
• Kuan-Yu Liao, Chia-Yuan Chang, James Chien-Mo Li:
  A Parallel Test Pattern Generation Algorithm to Meet Multiple Quality Objectives. 1767-1772
  

Volume 30, Number 12, 2011

• Sheng Yang, S. Saqib Khursheed, Bashir M. Al-Hashimi, David Flynn, Sachin Idgunji:
  Reliable State Retention-Based Embedded Processors Through Monitoring and Recovery. 1773-1785
  
• Tsung-Wei Huang, Shih-Yuan Yeh, Tsung-Yi Ho:
  A Network-Flow Based Pin-Count Aware Routing Algorithm for Broadcast-Addressing EWOD Chips. 1786-1799
  
• Kyosun Kim, Sangho Shin, Sung-Mo Kang:
  Field Programmable Stateful Logic Array. 1800-1813
  
• Wangyang Zhang, Xin Li, Frank Liu, Emrah Acar, Rob A. Rutenbar, Ronald D. Blanton:
  Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. 1814-1827
  
• Roxana Ionutiu, Joost Rommes, Wil H. A. Schilders:
  SparseRC: Sparsity Preserving Model Reduction for RC Circuits With Many Terminals. 1828-1841
  
• Muhammet Mustafa Ozdal, Renato Fernandes Hentschke:
  An Algorithmic Study of Exact Route Matching for Integrated Circuits. 1842-1855
  
• Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang:
  Pulsed-Latch Aware Placement for Timing-Integrity Optimization. 1856-1869
  
• Mark Po-Hung Lin, Chih-Cheng Hsu, Yao-Tsung Chang:
  Post-Placement Power Optimization With Multi-Bit Flip-Flops. 1870-1882
  
• Mohamed M. Sabry, Ayse Kivilcim Coskun, David Atienza, Tajana Simunic Rosing, Thomas Brunschwiler:
  Energy-Efficient Multiobjective Thermal Control for Liquid-Cooled 3-D Stacked Architectures. 1883-1896
  
• Yu-Hsiang Kao, Ming Yang, N. Sertac Artan, H. Jonathan Chao:
  CNoC: High-Radix Clos Network-on-Chip. 1897-1910
  
• Daniel Arumí, Rosa Rodríguez Montanes, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman:
  Diagnosis of Interconnect Full Open Defects in the Presence of Fan-Out. 1911-1922
  
• Junxia Ma, Mohammad Tehranipoor:
  Layout-Aware Critical Path Delay Test Under Maximum Power Supply Noise Effects. 1923-1934
  

Last update Fri May 24 20:51:46 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page