IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 6

Volume 6, Number 1, January 1987

• K. C.-K. Weng, Ping Yang, Jue-Hsien Chern:
  A Predictor/CAD Model for Buried-Channel MOS Transistors. 4-16
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• C. Andrew Neff, Ravi Nair:
  A Ranking Algorithm for MOS Circuit Layouts. 17-21
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• Rajiv Kane, Sartaj K. Sahni:
  A Systolic Design-Rule Checker. 22-32
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• Dan I. Moldovan:
  ADVIS: A Software Package for the Design of Systolic Arrays. 33-40
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• Zhiping Yu, Robert W. Dutton, Massimo Vanzi:
  An Extension to Newton's Method in Device Simulators--On An Efficient Algorithm to Evaluate Small-Signal Parameters and to Predict Initial Guess. 41-45
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• Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Nobuhiko Koike, Kenji Ohmori:
  Block-Level Hardware Logic Simulation Machine. 46-54
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• Maciej J. Ciesielski, E. Kinnen:
  Digraph Relaxation for 2-Dimensional Placement of IC Blocks. 55-66
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• K. C. Chang, David Hung-Chang Du:
  Efficient Algorithms for Layer Assignment Problem. 67-78
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• Narsingh Deo, Mukkai S. Krishnamoorthy, Michael A. Langston:
  Exact and Approximate Solutions for the Gate Matrix Layout Problem. 79-84
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• Silvano Gai, Fabio Somenzi, M. Spalla:
  Fast and Coherent Simulation with Zero Delay Elements. 85-93
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• Kenneth J. Supowit:
  Finding a Maximum Planar Subset of a Set of Nets in a Channel. 93-94
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• Sangyong Han, Sartaj K. Sahni:
  Layering Algorithms For Single-Row Routing. 95-102
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• Donald E. Thomas, Robert L. Blackburn, Jayanth V. Rajan:
  Linking the Behavioral and Structural Domains of Representation for Digital System Design. 103-110
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• Issac L. Bain, Lance A. Glasser:
  Methodology Verification of Hierarchically Described VLSI Circuits. 111-115
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• K. S. Kumar, J. H. Tracey:
  Modeling and Description of Processor-Based Systems with DTMSII. 116-127
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• Vasant B. Rao, Timothy N. Trick:
  Network Partitioning and Ordering for MOS VLSI Circuits. 128-144
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• K. Komatsu, M. Suzuki:
  The Outline Procedure in Pattern Data Preparation for Vector-Scan Electron-Beam Lithography. 145-151
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Volume 6, Number 2, March 1987

• Takashi Fujii, Hideya Horikawa, Tohru Kikuno, Noriyoshi Yoshida:
  A Heuristic Algorithm for Gate Assignment in One-Dimensional Array Approach. 159-164
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• Ravi Nair:
  A Simple Yet Effective Technique for Global Wiring. 165-172
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• Hiroshi Iwai, Mark R. Pinto, Conor S. Rafferty, J. E. Oristian, Robert W. Dutton:
  Analysis of Velocity Saturation and Other Effects on Short-Channel MOS Transistor Capacitances. 173-184
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• A. Akiyama, T. Hosoi, I. Ishihara, S. Matsumoto, T. Niimi:
  Computer Simulation of Impurity Diffusion in Semiconductors by the Monte Carlo Method. 185-189
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• David Hung-Chang Du, Oscar H. Ibarra, J. Fernando Naveda:
  Single-Row Routing with Crossover Bound. 190-201
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• Kevin S. B. Szabo, James M. Leask, Mohamed I. Elmasry:
  Symbolic Layout for Bipolar and MOS VLSI. 202-210
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• Patrick Siarry, L. Bergonzi, Gérard Dreyfus:
  Thermodynamic Optimization of Block Placement. 211-221
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• Chin-Long Wey, Fabrizio Lombardi:
  On the Repair of Redundant RAM's. 222-231
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• Chi-Yuan Lo, Hao N. Nham, Ajoy K. Bose:
  Algorithms for an Advanced Fault Simulation System in MOTIS. 232-240
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• T. Watanabe, H. Kitazawa, Y. Sugiyama:
  A Parallel Adaptable Routing Algorithm and its Implementation on a Two-Dimensional Array Processor. 241-250
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• Ibrahim N. Hajj, Daniel G. Saab:
  Switch-Level Logic Simulation of Digital Bipolar Circuits. 251-258
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• Howard Trickey:
  Flamel: A High-Level Hardware Compiler. 259-269
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• Nils Hedenstierna, Kjell O. Jeppson:
  CMOS Circuit Speed and Buffer Optimization. 270-281
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• Rolf Sundblad, Christer Svensson:
  Fully Dynamic Switch-Level Simulation of CMOS Circuits. 282-289
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• Yiu Kei Li, J. P. Robinson:
  Space Compression Methods With Output Data Modification. 290-294
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Volume 6, Number 3, May 1987

• Masaharu Hirayama:
  A Silicon Compiler System Based on Asynchronous Architecture. 297-304
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• Nagisa Ishiura, Hiroto Yasuura, Shuzo Yajima:
  High-Speed Logic Simulation on Vector Processors. 305-321
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• Yukihiro Nakamura:
  An Integrated Logic Design Environment Based on Behavioral Description. 322-336
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• Takashi Mitsuhashi, Kenji Yoshida:
  A Resistance Calculation Algorithm and Its Application to Circuit Extraction. 337-345
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• M. Terai, Y. Ajioka, T. Noda, M. Ozaki, T. Umeki, K. Sato:
  Symbolic Layout System: Application Results and Functional Improvements. 346-354
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• Gotaro Odawara, Takahisa Hiraide, Osamu Nishina:
  Partitioning and Placement Technique for CMOS Gate Arrays. 355-363
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• Atsushi Kurosawa, Kazutaka Yamada, Aritoyo Kishimoto, Kunio Mori, Nobuyuki Nishiguchi:
  A Practical CAD System Application for Full Custom VLSI Microcomputer Chips. 364-373
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• Masaki Ishikawa, T. Matsuda, T. Yoshimura, Satoshi Goto:
  Compaction-Based Custom LSI Layout Design Method. 374-382
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• Masahiro Fukui, A. Yamamoto, R. Yamaguchi, Sigeru Hayama, Y. Mano:
  A Block Interconnection Algorithm for Hierarchical Layout System. 383-391
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• Takao Nishida, Shunsuke Miyamoto, Tokinori Kozawa, Katsuya Satoh:
  RFSIM: Reduced Fault Simulator. 392-402
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• Yoshihiko Hirai, Masaru Sasago, Masayuki Endo, K. Tsuji, Yojiro Mano:
  Process Modeling for Photoresist Development and Design of DLR/sd (Double-Layer Resist by a Single Development) Process. 403-409
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• S. Isomae, S. Yamamoto:
  A New Two-Dimensional Silicon Oxidation Model. 410-416
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• S. Yamamoto, T. Kure, M. Ohgo, Teruo Matsuzawa, S. Tachi, H. Sunami:
  A Two-Dimensional Etching Profile Simulator: ESPRIT. 417-422
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• Y. Ohkura, Toru Toyabe, H. Masuda:
  Analysis of MOSFET Capacitances and Their Behavior at Short-Channel Lengths Using an AC Device Simulator. 423-430
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• A. Moniwa, Teruo Matsuzawa, T. Ito, H. Sunami:
  A Three-Dimensional Photoresist Imaging Process Simulator for Strong Standing-Wave Effect Environment. 431-438
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• M. Ohgo, Y. Takano, A. Moniwa, S. Yamamoto, Y. Sakai, H. Masuda, H. Sunami:
  A Two-Dimensional Integrated Process Simulator: SPIRIT-I. 439-445
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• Teruo Matsuzawa, A. Moniwa, N. Hasegawa, H. Sunami:
  Two-Dimensional Simulation of Photolithography on Reflective Stepped Substrate. 446-451
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• Yukio Aoki, Hiroo Masuda, Shozo Shimada, Shoji Sato:
  A New Design-Centering Methodology for VLSI Device Development. 452-461
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• Yoichi Shiraishi, Jun'ya Sakemi:
  A Permeation Router. 462-471
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• Rakesh Chadha, Kishore Singhal, Jiri Vlach, Ernst Christen, Milan Vlach:
  WATOPT -- An Optimizer for Circuit Applications. 472-479
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• Norman P. Jouppi:
  Derivation of Signal Flow Direction in MOS VLSI. 480-490
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Volume 6, Number 4, July 1987

• Vijay Pitchumani, Qisui Zhang:
  A Mixed HVH-VHV Algorithm for Three-Layer Channel Routing. 497-502
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• Majid Sarrafzadeh:
  Channel-Routing Problem in the Knock-Knee Mode Is NP-Complete. 503-506
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• A. Margarino, A. Romano, A. De Gloria, Francesco Curatelli, P. Antognetti:
  A Tile-Expansion Router. 507-517
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• W. K. Luk, Paolo Sipala, Markku Tamminen, Donald T. Tang, Lin S. Woo, Chak-Kuen Wong:
  A Hierarchical Global Wiring Algorithm for Custom Chip Design. 518-533
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• Saul A. Kravitz, Rob A. Rutenbar:
  Placement by Simulated Annealing on a Multiprocessor. 534-549
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• Malgorzata Marek-Sadowska:
  Pad Assignment for Power Nets in VLSI Circuits. 550-560
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• Hossein Modarres, Ronald J. Lomax:
  A Formal Approach to Design-Rule Checking. 561-573
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• Philip C. Chan, R. Liu, S. K. Lau, Mario Pinto-Guedes:
  A Subthreshold Conduction Model for Circuit Simulation of Submicron MOSFET. 574-581
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• M. C. Hsu, Bing J. Sheu:
  Inverse-Geometry Dependence of MOS Transistor Electrical Parameters. 582-585
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• S. L. Wong, C. Andre T. Salama:
  Improved Simulation of p- and n-channel MOSFET's Using an Enhanced SPICE MOS3 Model. 586-591
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• Ihao Chen, Andrzej J. Strojwas:
  A Methodology for Optimal Test Structure Design for Statistical Process Characterization and Diagnosis. 592-600
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• Zeev Barzilai, J. Lawrence Carter, Barry K. Rosen, Joe D. Rutledge:
  HSS--A High-Speed Simulator. 601-617
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• Randal E. Bryant:
  Algorithmic Aspects of Symbolic Switch Network Analysis. 618-633
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• Randal E. Bryant:
  Boolean Analysis of MOS Circuits. 634-649
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• Norman P. Jouppi:
  Timing Analysis and Performance Improvement of MOS VLSI Designs. 650-665
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• Sumit Ghosh:
  A Distributed Approach to Timing Verification of Synchronous and Asynchronous Digital Designs. 666-677
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• R. J. Bowman, C. C. Brewster:
  Determining the Zeros and Poles of Linear Circuit Networks Using Function Approximation. 678-690
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Volume 6, Number 5, September 1987

• Chin Jen Lin, Sudhakar M. Reddy:
  On Delay Fault Testing in Logic Circuits. 694-703
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• Kurt Antreich, Michael H. Schulz:
  Accelerated Fault Simulation and Fault Grading in Combinational Circuits. 704-712
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• Abhijit Chatterjee, Jacob A. Abraham:
  On the C-Testability of Generalized Counters. 713-726
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• Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli:
  Multiple-Valued Minimization for PLA Optimization. 727-750
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• Giovanni De Micheli:
  Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits. 751-765
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• Douglas S. Reeves, Mary Jane Irwin:
  Fast Methods for Switch-Level Verification of MOS Circuits. 766-779
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• Erik C. Carlson, Rob A. Rutenbar:
  A Scanline Data Structure Processor for VLSI Geometry Checking. 780-794
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• Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman:
  Optimal Chaining of CMOS Transistors in a Functional Cell. 795-801
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• D. K. Hwang, W. Kent Fuchs, Sung-Mo Kang:
  An Efficient Approach to Gate Matrix Layout. 802-809
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• K. Winter, Dieter A. Mlynski:
  Hierarchical Loose Routing for Gate Arrays. 810-819
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• Gregory B. Sorkin:
  Asymptotically Perfect Trivial Global Routing: A Stochastic Analysis. 820-827
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• Wayne Wei-Ming Dai, Ernest S. Kuh:
  Simultaneous Floor Planning and Global Routing for Hierarchical Building-Block Layout. 828-837
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• Andrea Casotto, Fabio Romeo, Alberto L. Sangiovanni-Vincentelli:
  A Parallel Simulated Annealing Algorithm for the Placement of Macro-Cells. 838-847
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• William A. Rogers, John F. Guzolek, Jacob A. Abraham:
  Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. 848-862
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• Jürgen Doenhardt, Thomas Lengauer:
  Algorithmic Aspects of One-Dimensional Layout Compaction. 863-878
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• Antonio Gnudi, Paolo Ciampolini, Roberto Guerrieri, Massimo Rudan, Giorgio Baccarani:
  Sensitivity Analysis for Device Design. 879-885
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• Sung-Mo Kang:
  Metal--Metal Matrix (M /sup 3/) for High-Speed MOS VLSI Layout. 886-891
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• Donald L. Dietmeyer:
  Local Transformations via Cube Operations. 892-902
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• Jin-fuw Lee, Donald T. Tang:
  VLSI Layout Compaction with Grid and Mixed Constraints. 903-910
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Volume 6, Number 6, November 1987

• Srinivas Devadas, A. Richard Newton:
  Topological Optimization of Multiple-Level Array Logic. 915-941
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• Hyunchul Shin, Alberto L. Sangiovanni-Vincentelli:
  A Detailed Router Based on Incremental Routing Modifications: Mighty. 942-955
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• James P. Cohoon, William D. Paris:
  Genetic Placement. 956-964
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• Ihao Chen, Andrzej J. Strojwas:
  Realistic Yield Simulation for VLSIC Structural Failures. 965-980
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• Robert F. Lucas, Tom Blank, Jerome J. Tiemann:
  A Parallel Solution Method for Large Sparse Systems of Equations. 981-991
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• Dundar Dumlugol, Patrick Odent, Johan Cockx, Hugo De Man:
  Switch-Electrical Segmented Waveform Relaxation for Digital MOS VLSI and Its Acceleration on Parallel Computers. 992-1005
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• Silvano Gai, Fabio Somenzi, Ernst Ulrich:
  Advances in Concurrent Multilevel Simulation. 1006-1012
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• Tat-Kwan Yu, Sung-Mo Kang, I. N. Haji, Timothy N. Trick:
  Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI. 1013-1022
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• Joseph E. Hall, Dale E. Hocevar, Ping Yang, Michael J. McGraw:
  SPIDER -- A CAD System for Modeling VLSI Metallization Patterns. 1023-1031
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• J. Mar, Krish Bhargavan, Steven G. Duvall, Ram Firestone, Dennis J. Lucey, S. N. Nandgaonkar, S. Wu, Kaung-Shia Yu, F. Zarbakhsh:
  EASE--An Application-Based CAD System for Process Design. 1032-1038
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• Jacques Benkoski, Andrzej J. Strojwas:
  A New Approach to Hierarchical and Statistical Timing Simulations. 1039-1052
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• Chorng-Yeong Chu, Mark Horowitz:
  Charge-Sharing Models for Switch-Level Simulation. 1053-1061
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• Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang:
  MIS: A Multiple-Level Logic Optimization System. 1062-1081
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• Robert Lisanke, Franc Brglez, Aart J. de Geus, David Gregory:
  Testability-Driven Random Test-Pattern Generation. 1082-1087
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• Gabriele Saucier, Michel Crastes de Paulet, P. Sicard:
  ASYL: A Rule-Based System for Controller Synthesis. 1088-1097
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• Barry M. Pangrle, Daniel D. Gajski:
  Design Tools for Intelligent Silicon Compilation. 1098-1112
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