Volume 7, Number 1, January 1988
: A design of programmable logic arrays with random pattern-testability.
: Analysis and proposal of signature circuits for LSI testing.
Niraj K. Jha
: Testing for multiple faults in domino-CMOS logic circuits.
Volume 7, Number 2, February 1988
Francisco A. Leon
: Numerical modeling of glass flow and spin-on planarization.
: Line-to-ground capacitance calculation for VLSI: a comparison.
Volume 7, Number 3, March 1988
, Uri M. Ascher
: Model and solution strategy for placement of rectangular blocks in the Euclidean plane.
Volume 7, Number 4, April 1988
: On yield consideration for the design of redundant programmable logic arrays.
Volume 7, Number 5, May 1988
Volume 7, Number 6, June 1988
Volume 7, Number 7, July 1988
Steven G. Duvall
: An interchange format for process and device simulation.
: Generalized Manhattan path algorithm with applications.
Volume 7, Number 8, August 1988
: Extraction of BJT model parameters using optimization method.
Rex E. Lowther
: The solution of a numerical problem encountered when adding a mobility model to a finite-element device simulator.
Volume 7, Number 9, September 1988
Andrew W. Appel
: Simulating digital circuits with one bit per wire.
Volume 7, Number 10, October 1988
Wolfgang O. Budde
: Modular testprocessor for VLSI chips and high-density PC boards.
Volume 7, Number 11, November 1988
David M. Lewis
: Hardware accelerators for timing simulation of VLSI digital circuits.
: A new framework of design rules for compaction of VLSI layouts.
Hwan Gue Cho
, C. M. Kyung
: A heuristic standard cell placement algorithm using constrained multistage graph model.
Sharon R. Perkins
, Tom Rhyne
: An algorithm for identifying and selecting the primed implicants of a multiple-output Boolean function.
Volume 7, Number 12, December 1988
Leo R. Piotrowski
: An improved Spice2 Zener diode model for soft-region simulation capability.