Volume 8, Number 1, January 1989
S. S.-S. Chung: A charge-based capacitance model of short-channel MOSFETs. 1-7- Young Hwan Kim, Seung Ho Hwang, A. Richard Newton: Electrical-logic simulation and its applications. 8-22
- Kenji Nishi, Kouichi Sakamoto, Shigeki Kuroda, Jun Ueda, Tatsurou Miyoshi, Shintaro Ushio: A general-purpose two-dimensional process simulator-OPUS for arbitrary structures. 23-32
- Pramod V. Argade: Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS. 33-40
- John Horan, Colin Lyden, Alan Mathewson, Ciaran G. Cahill, W. A. Lane: Analysis of distributed resistance effects in MOS transistors. 41-45
- Andrzej Krasniewski, Slawomir Pilarski: Circular self-test path: a low-cost BIST technique for VLSI circuits. 46-55
- Wing Ning Li, Sudhakar M. Reddy, Sartaj K. Sahni: On path selection in combinational logic circuits. 56-63
- Gary D. Hachtel, Christopher R. Morrison: Linear complexity algorithms for hierarchical routing. 64-80
- Susheel J. Chandra, Janak H. Patel: Experimental evaluation of testability measures for test generation (logic circuits). 93-97
Volume 8, Number 2, February 1989
- Gerhard Tröster, Peter Tomaszewski: Mismatch simulation for layout sensitive parameters of IC components and devices. 101-107
- Eddie van Schie, Jan Middelhoek: Two methods to improve the performance of Monte Carlo simulations of ion implantation in amorphous targets. 108-113
- Linda S. Milor, V. Visvanathan: Detection of catastrophic faults in analog integrated circuits. 114-130
- Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal: A directed search method for test generation using a concurrent simulator. 131-138
- Shmuel Wimer, Israel Koren, Israel Cederbaum: Optimal aspect ratios of building blocks in VLSI. 139-145
- Gopalakrishnan Vijayan, H. H. Chen, Chak-Kuen Wong: On VHV-routing in channels with irregular boundaries. 146-152
- Rainer Amann, Utz G. Baitinger: Optimal state chains and state codes in finite state machines. 153-170
- Hi-Keung Tony Ma, Srinivas Devadas, Ruey-Sing Wei, Alberto L. Sangiovanni-Vincentelli: Logic verification algorithms and their parallel implementation. 181-189
Volume 8, Number 3, March 1989
- M. Sytrzycki: Modeling of gate oxide shorts in MOS transistors. 193-202
- Michael Nicolaidis: Self-exercising checkers for unified built-in self-test (UBIST). 203-218
- Teofilo F. Gonzalez, Shashishekhar Kurki-Gowdara: An approximation algorithm for the via placement problem. 219-228
- Ludo Weyten, Wim De Pauw: Quad list quad trees: a geometrical data structure with improved performance for large region queries. 229-233
- Peter Ramyalal Suaris, Gershon Kedem: A quadrisection-based combined place and route scheme for standard cells. 234-244
- R. Jayakumar, Krishnaiyan Thulasiraman, M. N. S. Swamy: O(n2) algorithms for graph planarization. 257-267
- Michel Dagenais, Nicholas C. Rumin: On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. 268-278
- Michael L. Bushnell, Stephen W. Director: Automated design tool execution in the Ulysses design environment. 279-287
- Wayne Wolf: How to build a hardware description and measurement system on an object-oriented programming language. 288-301
- Evangelos Simoudis: A knowledge-based system for the evaluation and redesign of digital circuit networks. 302-315
- El-Sayed A. Talkhan, Aly M. H. Ahmed, Aly E. Salama: Microprocessors functional testing techniques. 316-318
Volume 8, Number 4, April 1989
- Scott H. Goodwin-Johansson, Ravi Subrahmanyan, Carey E. Floyd, Hisham Z. Massoud: Two-dimensional impurity profiling with emission computed tomography techniques. 323-335
- Brian J. Mulvaney, Walter B. Richardson, Timothy L. Crandle: PEPPER-a process simulator for VLSI. 336-349
- Robert Anholt, Thomas W. Sigmon: A process and device model for GaAs MESFET technology: GATES. 350-359
- Franco Venturi, R. Kent Smith, Enrico Sangiorgi, Mark R. Pinto, Bruno Riccò: A general purpose device simulator coupling Poisson and Monte Carlo transport with applications to deep submicron MOSFETs. 360-369
- Chang G. Hwang, Robert W. Dutton: Improved physical modeling of submicron MOSFETs based on parameter extraction using 2-D simulation. 370-379
- William M. Coughran Jr., Wolfgang Fichtner, Eric Grosse: Extracting transistor changes from device simulations by gradient fitting. 380-394
- Walter R. Curtice: Intrinsic GaAs MESFET equivalent circuit models generated from two-dimensional simulations. 395-402
- Chang-Sheng Ying, Joshua Sook-Leung Wong: An analytical approach to floorplanning for hierarchical building blocks layout [VLSI]. 403-412
- David N. Deutsch: Two new and 'more difficult' channel routing problems. 448
Volume 8, Number 5, May 1989
- Gerhard Hobler, Siegfried Selberherr: Monte Carlo simulation of ion implantation into two- and three-dimensional structures. 450-459
- Martin D. Giles: Defect-coupled diffusion at high concentrations. 460-467
- Gen-Lin Tan, Xiao-Li Yuan, Qi-Ming Zhang, Walter H. Ku, An-Jui Shey: Two-dimensional semiconductor device analysis based on new finite-element discretization employing the S-G scheme. 468-478
- Josef F. Burgler, Randolph E. Bank, Wolfgang Fichtner, R. Kent Smith: A new discretization scheme for the semiconductor current continuity equations. 479-489
- Paolo Ciampolini, Alessandro Forghieri, Anna Pierantoni, Antonio Gnudi, Massimo Rudan, Giorgio Baccarani: Adaptive mesh generation preserving the quality of the initial grid. 490-500
- Carl L. Gardner, Joseph W. Jerome, Donald J. Rose: Numerical methods for the hydrodynamic device model: subsonic flow. 501-507
- Thomas D. Linton Jr., P. A. Blakey: A fast, general three-dimensional device simulator and its application in a submicron EPROM design study. 508-515
- Jue-Hsien Chern, John T. Maeda, Lawrence A. Arledge Jr., Ping Yang: SIERRA: a 3-D device simulator for reliability modeling. 516-527
- Ke-Chih Wu, Robert F. Lucas, Ze-Yi Wang, Robert W. Dutton: New approaches in a 3-D one-carrier device solver. 528-537
- Hal R. Yeager, Robert W. Dutton: Improvement in norm-reducing Newton methods for circuit simulation. 538-546
- Youn-Sik Hong, Kyu Ho Park, Myunghwan Kim: A heuristic algorithm for ordering the columns in one-dimensional logica arrays. 547-562
- Niraj K. Jha: Separable codes for detecting unidirectional errors. 571-574
- J. T. Mowchenko: A lower bound on channel density after global routing. 574-577
Volume 8, Number 6, June 1989
- Mahesh Sharma, Graham F. Carey: Semiconductor device simulation using adaptive refinement and flux upwinding. 590-598
- Hiroyuki Umimoto, Shinji Odanaka, Ichiro Nakao, Hideya Esaki: Numerical modeling of nonplanar oxidation coupled with stress effects. 599-607
- Guang-Wen Pan, Kenneth S. Olson, Barry K. Gilbert: Improved algorithmic methods for the prediction of wavefront propagation behavior in multiconductor transmission lines for high frequency digital signal processors. 608-621
- Shoichiro Yamada, Hirokai Okude, Tamotsu Kasai: A hierarchical algorithm for one-dimensional gate assignment based on contraction of nets. 622-629
- S. Chowdhury: Analytical approaches to the combinatorial optimization in linear placement problems. 630-639
- Kuang-Wei Chiang, Surendra Nahar, Chi-Yuan Lo: Time-efficient VLSI artwork analysis algorithms in GOALIE2. 640-648
- Toshiaki Tanaka, Tsutomu Kobayashi, Osamu Karatsu: HARP: FORTRAN to silicon [compilation system]. 649-660
- Pierre G. Paulin, John P. Knight: Force-directed scheduling for the behavioral synthesis of ASICs. 661-679
- Fathey M. El-Turky, Elizabeth E. Perry: BLADES: an artificial intelligence approach to analog circuit design. 680-692
- Per Andersson, Lars H. Philipson: Movie-an interactive environment for silicon compilation tools. 693-701
- Maciej J. Ciesielski: Layer assignment for VLSI interconnect delay minimization. 702-707
Volume 8, Number 7, July 1989
- Paul J. V. Vandeloo, Willy M. C. Sansen: Modeling of the MOS transistor for high frequency analog design. 713-723
- Shiuh-Wuu Lee: Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling. 724-730
- Niraj K. Jha: A totally self-checking checker for Borden's code. 731-736
- Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer: Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation. 737-743
- Charles J. Poirier: Excellerator: custom CMOS leaf cell layout generator. 744-755
- Srinivas Devadas, A. Richard Newton: Algorithms for hardware allocation in data path synthesis. 768-781
- Min-You Wu, Ibrahim N. Hajj: Switching network logic approach to sequential MOS circuit design. 782-794
- H. Cai: On empty rooms in floorplan graphics: comments on a deficiency in two papers. 795-797
- Rochit Rajsuman, Yashwant K. Malaiya, Anura P. Jayasumana: Limitations of switch level analysis for bridging faults. 807-811
- Michael H. Schulz, Elisabeth Auth: Improved deterministic test pattern generation with applications to redundancy identification. 811-816
- H. L. Kwok: Threshold voltage for GaAs MESFET with a recoil-implanted channel profile. 817-820
Volume 8, Number 8, August 1989
- John R. F. McMacken, Savvas G. Chamberlain: CHORD: a modular semiconductor device simulation development tool incorporating external network models. 826-836
- Rex E. Lowther: A discretization scheme that allows coarse grid-spacing in finite-difference process simulation. 837-841
- Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. M. Miller, Howard C. Card: Cellular automata-based pseudorandom number generators for built-in self-test. 842-859
- Ravi Nair, C. Leonard Berman, Peter S. Hauge, Ellen J. Yoffa: Generation of performance constraints for layout. 860-874
- Devadas Varma, E. A. Trachtenberg: Design automation tools for efficient implementation of logic functions by decomposition. 901-916
- Jitender S. Deogun, Bhargab B. Bhattacharya: Via minimization in VLSI routing with movable terminals. 917-920
- José Pineda de Gyvez, Jochen A. G. Jess: On the design and implementation of a wafer yield editor. 920-925
- Wayne Wolf, Kurt Keutzer, Janaki Akella: Addendum to 'A kernel-finding state assignment algorithm for multi-level logic'. 925-927
- George W. Rhyne, Michael Steer, K. S. Kundent, Alberto L. Sangiovanni-Vincentelli: Comments on 'Simulation of nonlinear circuits in the frequency domain' [with reply]. 927-929
- James B. Kuo, G. P. Rosseel, Robert W. Dutton: Two-dimensional analysis of a merged BiPMOS device. 929-932
Volume 8, Number 9, September 1989
- Bharat L. Bhuva, John J. Paulos, Ronald S. Gyurcsik, Sherra E. Kerns: Switch-level simulation of total dose effects on CMOS VLSI circuits. 933-938
- Michael D. Deal, S. E. Hansen, Thomas W. Sigmon: SUPREM 3.5-process modeling of GaAs integrated circuit technology. 939-951
- Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli: Reconfiguration of VLSI arrays by covering. 952-965
- Sreejit Chakravarty: On the complexity of computing tests for CMOS gates. 973-980
- I. Vandeweerd, Kris Croes, Luc Rijnders, Paul Six, Hugo De Man: REDUSA: module generation by automatic elimination of superfluous blocks in regular structures. 989-998
- J. E. (Ned) Lecky, O. J. Murphy, Richard Absher: Graph theoretic algorithms for the PLA folding problem. 1014-1021
- Hideo Fujiwara: Enhancing random-pattern coverage of programmable logic arrays via masking technique. 1022-1025
- Çetin Kaya Koç, P. F. Ordung: Schwarz-Christoffel transformation for the simulation of two-dimensional capacitance [VLSI circuits]. 1025-1027
- Young-Hyun Jun, Ki Jun, Song-Bai Park: An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation. 1027-1032
Volume 8, Number 10, October 1989
- Mehmet A. Cirit: The Meyer model revisited: why is charge not conserved? [MOS transistor]. 1033-1037
- James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley: Two-dimensional transient analysis of a collector-up ECL inverter. 1038-1045
- Naoyuki Shigyo, T. Wada, Seiji Yasuda: Discretization problem for multidimensional current flow. 1046-1050
- Paul F. Cox, Richard Burch, Ping Yang, Dale E. Hocevar: New implicit integration method for efficient latency exploitation in circuit simulation. 1051-1064
- André Ivanov, Vinod K. Agarwal: An analysis of the probabilistic behavior of linear feedback signature registers. 1074-1088
- James L. Olivier, Füsun Özgüner: Design of concurrent error-detecting systolic arrays using |g 3N|M codes. 1089-1099
- Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli: A synthesis and optimization procedure for fully and easily testable sequential machines. 1100-1107
- Robert A. Walker, Donald E. Thomas: Behavioral transformation for algorithmic level IC design. 1115-1128
Volume 8, Number 11, November 1989
- Maurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò: An analytical model for the aliasing probability in signature analysis testing. 1133-1144
- Chantal Robach, Daniel Lutoff, Nouar Garcia: Knowledge-based functional specification of test and maintenance programs. 1145-1156
- Anucha Pitaksanonkul, Suchai Thanawastien, Chidchanok Lursinsap: Comparisons of quad trees and 4-D trees: new results [VLSI layout]. 1157-1164
- Chong S. Rim, Toshinobu Kashiwabara, Kazuo Nakajima: Exact algorithms for multilayer topological via minimization. 1165-1173
- Teresa H. Y. Meng, Robert W. Brodersen, David G. Messerschmitt: Automatic synthesis of asynchronous circuits from high-level specifications. 1185-1205
- Srinivas Devadas, A. Richard Newton: Decomposition and factorization of sequential finite state machines. 1206-1217
- Ludo Weyten, Wim De Pauw: Performance prediction for adaptive quad tree graphical data structures. 1218-1222
- Sandip Kundu: Design of multioutput CMOS combinational logic circuits for robust testability. 1222-1226
Volume 8, Number 12, December 1989
- Miriam Leeser: Reasoning about the function and timing of integrated circuits with interval temporal logic. 1233-1246
- Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley: OASYS: a framework for analog circuit synthesis. 1247-1266
- Richard W. Linderman, Paul C. Rossbach, David M. Gallagher: Design and application of an optimizing XROM silicon compiler. 1267-1275
- P. Sadayappan, V. Visvanathan: Efficient sparse matrix factorization for circuit simulation on vector supercomputers. 1276-1285
- Resve A. Saleh, A. Richard Newton: The exploitation of latency and multirate behavior using nonlinear relaxation for circuit simulation. 1286-1298
- K. K. Low, Stephen W. Director: An efficient methodology for building macromodels of IC fabrication processes. 1299-1313
- Charles H. Stapper: Simulation of spatial fault distributions for integrated circuit yield estimations. 1314-1318
- Armen H. Zemanian, Reginald P. Tewarson, Chi Ping Ju, Juif Frank Jen: Three-dimensional capacitance computations for VLSI/ULSI interconnections. 1319-1326
- Noriyoshi Itazaki, Kozo Kinoshita: Test pattern generation for circuits with tri-state modules by Z-algorithm. 1327-1334
- Wayne Wei-Ming Dai: Hierarchical placement and floorplanning in BEAR. 1335-1349
- Raja Daoud, Füsun Özgüner: Highly vectorizable fault simulation on the Cray X-MP supercomputer. 1362-1365
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