Transactions on High-Performance Embedded Architectures and Compilers, Volume 3, 2011

Per Stenström (Ed.): Transactions on High-Performance Embedded Architectures and Compilers III. Lecture Notes in Computer Science 6590 Springer 2011, ISBN 978-3-642-19447-4

Third International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC)

Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Dynamic Cache Partitioning Based on the MLP of Cache Misses. 3-23
Chun-Chieh Lin, Chuen-Liang Chen:
Cache Sensitive Code Arrangement for Virtual Machine. 24-42
Subhradyuti Sarkar, Dean M. Tullsen:
Data Layout for Cache Performance on a Multithreaded Architecture. 43-68
Yiannakis Sazeides, Andreas Moustakas, Kypros Constantinides, Marios Kleanthous:
Improving Branch Prediction by Considering Affectors and Affectees Correlations. 69-88

Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete:
Eighth MEDEA Workshop. 91-92
Matthias A. Blumrich, Valentina Salapura, Alan Gara:
Exploring the Architecture of a Stream Register-Based Snoop Filter. 93-114
Fernando Latorre, Grigorios Magklis, José González, Pedro Chaparro, Antonio González:
CROB: Implementing a Large Instruction Window through Compression. 115-134
Isao Kotera, Kenta Abe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Power-Aware Dynamic Cache Partitioning for CMPs. 135-153
Jan Hoogerbrugge, Andrei Terechko:
A Multithreaded Multicore System for Embedded Media Processing. 154-173

Tarik Saidani, Lionel Lacassagne, Joel Falcou, Claude Tadonki, Samir Bouaziz:
Parallelization Schemes for Memory Optimization on the Cell Processor: A Case Study on the Harris Corner Detector. 177-200
Harald Devos, Jan Van Campenhout, Ingrid Verbauwhede, Dirk Stroobandt:
Constructing Application-Specific Memory Hierarchies on FPGAs. 201-216

Tobias Klug, Michael Ott, Josef Weidendorfer, Carsten Trinitis:
autopin - Automated Optimization of Thread-to-Core Pinning on Multicore Systems. 219-235
Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson:
Robust Adaptation to Available Parallelism in Transactional Memory Applications. 236-255
M. M. Waliullah:
Efficient Partial Roll-Backing Mechanism for Transactional Memory Systems. 256-274
Maziar Goudarzi, Tohru Ishihara, Hamid Noori:
Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies. 275-299

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