ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 11

Volume 11, Number 1, January 2006

• Nikil D. Dutt:
  Editorial. 1-2
  
• Tony Givargis:
  Zero cost indexing for improved processor cache performance. 3-25
  
• George A. Constantinides:
  Word-length optimization for differentiable nonlinear systems. 26-43
  
• Qing Su, Jamil Kawa, Charles Chiang, Yehia Massoud:
  Accurate modeling of substrate resistive coupling for floating substrates. 44-51
  
• Azadeh Davoodi, Ankur Srivastava:
  Effective techniques for the generalized low-power binding problem. 52-69
  
• Patrick Schaumont, Doris Ching, Ingrid Verbauwhede:
  An interactive codesign environment for domain-specific coprocessors. 70-87
  
• Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou:
  Reliable crosstalk-driven interconnect optimization. 88-103
  
• Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi:
  Compile-time area estimation for LUT-based FPGAs. 104-122
  
• Aviral Shrivastava, Partha Biswas, Ashok Halambi, Nikil D. Dutt, Alexandru Nicolau:
  Compilation framework for code size reduction using reduced bit-width ISAs (rISAs). 123-146
  
• Yi-Ping You, Chingren Lee, Jenq Kuen Lee:
  Compilers for leakage power reduction. 147-164
  
• Zili Shao, Bin Xiao, Chun Xue, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
  Loop scheduling with timing and switching-activity minimization for VLIW DSP. 165-185
  
• Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi:
  ILP models for simultaneous energy and transient power minimization during behavioral synthesis. 186-212
  
• Muhammet Mustafa Ozdal, Martin D. F. Wong:
  Two-layer bus routing for high-speed printed circuit boards. 213-227
  
• Mahmut T. Kandemir, J. Ramanujam, Ugur Sezer:
  Improving the energy behavior of block buffering using compiler optimizations. 228-250
  

Volume 11, Number 2, April 2006

• Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein:
  Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. 251-281
  
• Javed Absar, Francky Catthoor:
  Reuse analysis of indirectly indexed arrays. 282-305
  
• Ali Dasdan, Ivan Hom:
  Handling inverted temperature dependence in static timing analysis. 306-324
  
• Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Jinian Bian, Hannah Honghua Yang, Vijay Pitchumani:
  Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. 325-345
  
• Saravanan Padmanaban, Spyros Tragoudas:
  Implicit grading of multiple path delay faults. 346-361
  
• Deming Chen, Jason Cong, Junjuan Xu:
  Optimal simultaneous module and multivoltage assignment for low power. 362-386
  
• Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham:
  On the construction of zero-deficiency parallel prefix circuits with minimum depth. 387-409
  
• Mahmut T. Kandemir:
  Reducing energy consumption of multiprocessor SoC architectures by exploiting memory bank locality. 410-441
  
• Fei Su, Sule Ozev, Krishnendu Chakrabarty:
  Concurrent testing of digital microfluidics-based biochips. 442-464
  
• David Atienza, Jose Manuel Mendias, Stylianos Mamagkakis, Dimitrios Soudris, Francky Catthoor:
  Systematic dynamic memory management design methodology for reduced memory footprint. 465-489
  
• Wei Li, Daniel Blakely, Scott Van Sooy, Keven Dunn, David Kidd, Robert Rogenmoser, Dian Zhou:
  LVS verification across multiple power domains for a quad-core microprocessor. 490-500
  
• Jason A. Cheatham, John M. Emmert, Stanley Baumgart:
  A survey of fault tolerant methodologies for FPGAs. 501-533
  

Volume 11, Number 3, July 2006

• Massoud Pedram:
  Introduction to special issue: Novel paradigms in system-level design. 535-536
  
• Alessandro Pinto, Alvise Bonivento, Alberto L. Sangiovanni-Vincentelli, Roberto Passerone, Marco Sgroi:
  System level design paradigms: Platform-based design and communication synthesis. 537-563
  
• Radu Marculescu, Ümit Y. Ogras, Nicholas H. Zamora:
  Computation and communication refinement for multiprocessor SoC design: A system-level perspective. 564-592
  
• Paul Pop, Petru Eles, Zebo Peng, Traian Pop:
  Analysis and optimization of distributed real-time embedded systems. 593-625
  
• Prabhat Mishra, Aviral Shrivastava, Nikil Dutt:
  Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs. 626-658
  
• Roman L. Lysecky, Greg Stitt, Frank Vahid:
  Warp Processors. 659-681
  
• Fei Su, Krishnendu Chakrabarty:
  Module placement for fault-tolerant microfluidics-based biochips. 682-710
  
• Narender Hanchate, Nagarajan Ranganathan:
  A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. 711-739
  
• Gang Chen, Jason Cong:
  Simultaneous placement with clustering and duplication. 740-772
  
• Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan:
  A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. 773-796
  

Volume 11, Number 4, October 2006

• Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh:
  Postlayout optimization for synthesis of Domino circuits. 797-821
  
• André C. Nácul, Tony Givargis:
  Synthesis of time-constrained multitasking embedded software. 822-847
  
• Kunhyuk Kang, Bipul C. Paul, Kaushik Roy:
  Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters. 848-879
  
• Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu:
  Decomposition of instruction decoders for low-power designs. 880-889
  
• Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang:
  Crosstalk minimization in logic synthesis for PLAs. 890-915
  
• Sezer Gören, F. Joel Ferguson:
  Test sequence generation for controller verification and test with high coverage. 916-938
  
• Zhong-Zhen Wu, Shih-Chieh Chang:
  Multiple wire reconnections based on implication flow graph. 939-952
  
• Chi-Shong Wang, Chingwei Yeh:
  Performance-driven technology mapping with MSG partition and selective gate duplication. 953-973