ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 3

Volume 3, Number 1, January 1998

Eric W. Johnson, Jay B. Brockman:
Measurement and analysis of sequential design processes. 1-20
Karim Khordoc, Eduard Cerny:
Semantics and verification of action diagrams with linear timing. 21-50
Stan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, Srinivas Devadas:
A new viewpoint on code generation for directed acyclic graphs. 51-75
C.-J. Richard Shi, Janusz A. Brzozowski:
Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems. 76-107

Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen:
ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems. 109-135
Guido Araujo, Sharad Malik:
Code generation for fixed-point DSPs. 136-161
Giri Tiruvuri, Moon Chung:
Estimation of lower bounds in scheduling algorithms for high-level synthesis. 162-180
Frank Vahid, Thuy Dm Le, Yu-Chin Hsu:
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance. 181-208
Gernot Koch, Wolfgang Rosenstiel, Udo Kebschull:
Breakpoints and breakpoint detection in source-level emulation. 209-230
Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits. 231-248
Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi:
Structural diagnosis of interconnects by coloring. 249-271
Dinesh P. Mehta:
Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures. 272-284
Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. 285-307

Gianpiero Cabodi, Paolo Camurati, Stefano Quer:
Auxiliary variables for BDD-based representation and manipulation of Boolean functions. 309-340
Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao:
Bounded-skew clock and Steiner routing. 341-388
Wen-Ben Jone, K. S. Tsai:
Confidence analysis for defect-level estimation of VLSI random testing. 389-407
Anmol Mathur, Ali Dasdan, Rajesh K. Gupta:
Rate analysis for embedded systems. 408-436
Peichen Pan, C. L. Liu:
Optimal clock period FPGA technology mapping for sequential circuits. 437-462
Michael A. Riepe, Karem A. Sakallah:
The edge-based design rule model revisited. 463-486
Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee:
Eliminating false loops caused by sharing in control path. 487-495
Hai Zhou, D. F. Wong:
Optimal river routing with crosstalk constraints. 496-514

Claudio Passerone, Claudio Sansoè, Luciano Lavagno, Patrick C. McGeer, Jonathan Martin, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
Modeling reactive systems in Java. 515-523
Li-C. Wang, Magdy S. Abadir, Jing Zeng:
On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. 524-532
Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta:
A timing-driven design and validation methodology for embedded real-time systems. 533-553
Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee:
ATM switch design by high-level modeling, formal verification and high-level synthesi. 554-562
James K. Huggins, David Van Campenhout:
Specification and verification of pipelining in the ARM2 RISC microprocessor. 563-580
David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown:
High-level design verification of microprocessors via error modeling. 581-599
Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee:
Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. 600-625
Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda:
EXFI: a low-cost fault injection system for embedded microprocessor-based boards. 626-634