ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 4

Volume 4, Number 1, January 1999

Michael Gasteier, Manfred Glesner:
Bus-based communication synthesis on system level. 1-11
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer:
A text-compression-based method for code size minimization in embedded systems. 12-38
Xiaoyu Song, Yuke Wang:
On the crossing distribution problem. 39-51
Jyh-Mou Tseng, Jing-Yang Jou:
Two-level logic minimization for low power. 52-69
Frank Vahid:
Procedure cloning: a transformation for improved system-level functional partitioning. 70-96
Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly:
Power reduction and power-delay trade-offs using logic transformations. 97-121

Christoph Kern, Mark R. Greenstreet:
Formal verification in hardware design: a survey. 123-193
Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang:
BIFEST: a built-in intermediate fault effect sensing and test generation system for CMOS bridging faults. 194-218
Mitchell A. Thornton, V. S. S. Nair:
Behavioral synthesis of combinational logic using spectral-based heuristics. 219-230

Wei-Kai Cheng, Youn-Long Lin:
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. 231-256
Yau-Tsun Steven Li, Sharad Malik, Andrew Wolfe:
Performance estimation of embedded software with instruction cache modeling. 257-279
C.-J. Richard Shi, Michael W. Tian:
Simulation and sensitivity of linear analog circuits under parameter variations by Robust interval analysis. 280-312
Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich:
Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. 313-350

Luca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Riccardo Scarsi:
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers. 351-375
Kyumyung Choi, Steven P. Levitan:
A flexible datapath allocation method for architectural synthesis. 376-404
Inki Hong, Miodrag Potkonjak, Ramesh Karri:
Power optimization using divide-and-conquer techniques for minimization of the number of operations. 405-429
Miodrag Potkonjak, Wayne Wolf:
A methodology and algorithms for the design of hard real-time multitasking ASICs. 430-459