Volume 1, Number 1, March 1993
- Pallab K. Chatterjee, G. B. Larrabee:
Gigabit age microelectronics and their manufacture.
- Mario Kovac, N. Ranganathan, M. Varanasi:
SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm.
- Raja Venkateswaran, Pinaki Mazumder:
Coprocessor design for multilayer surface-mounted PCB routing.
- Fadi J. Kurdahi, Champaka Ramachandran:
Evaluating layout area tradeoffs for high level applications.
- Y. He, Ugur Çilingiroglu, Edgar Sánchez-Sinencio:
A high-density and low-power charge-based Hamming network.
- Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick:
A Monte Carlo approach for power estimation.
- John A. Nestor:
Visual register-transfer description of VLSI microarchitectures.
- H. Lin, Fabrizio Lombardi, M. Lu:
On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements.
Volume 1, Number 2, June 1993
- C. Sul, Robert D. McLeod, Witold Pedrycz:
Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays.
- S.-Y. Kuo, S.-C. Liang:
Design and analysis of defect tolerant hierarchical sorting networks.
- T.-Y. Wuu, Sarma B. K. Vrudhula:
A design of a fast and area efficient multi-input Muller C-element.
- Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya:
MARVLE: a VLSI chip for data compression using tree-based codes.
- Keshab K. Parhi, Takao Nishitani:
VLSI architectures for discrete wavelet transforms.
- A. Sharma, R. Jain:
Estimating architectural resources and performance for high-level synthesis applications.
- Joseph Varghese, Michael Butts, Jon Batcheller:
An efficient logic emulation system.
- Smaragda Konstantinidou:
The selective extra stage butterfly.
- Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.:
Modified Booth algorithm for high radix fixed-point multiplication.
- C.-S. Li, Harald S. Stone, Y. Kwark, C. M. Olsen:
Fully differential optical interconnections for high-speed digital systems.
- A. Chatterjee:
Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums.
- Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer:
Statistical timing analysis of combinational logic circuits.
- Jalil Fadavi-Ardekani:
M×N Booth encoded multiplier generator using optimized Wallace trees.
- Chris J. Myers, Teresa H. Y. Meng:
Synthesis of timed asynchronous circuits.
- Lishing Liu, Jih-Kwon Peir:
Cache sampling by sets.
- Tom Chen, Glen Sunada:
Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips.
Volume 1, Number 3, September 1993
- Reinaldo A. Bergamaschi, Andreas Kuehlmann:
A system for production use of high-level synthesis.
- J. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, Michael Payer, Michael Pilsl, S. Rumler, H. Soukup, Norbert Wehn, Peter Duzy:
The Siemens high-level synthesis system CALLAS.
- Catherine H. Gebotys:
Throughput optimized architectural synthesis.
- Ulrich Holtmann, Rolf Ernst:
Experiments with low-level speculative computation based on multiple branch prediction.
- Dave Filo, David C. Ku, Claudionor José Nunes Coelho Jr., Giovanni De Micheli:
Interface optimization for concurrent systems under timing constraints.
- D. Sreenivasa Rao, Fadi J. Kurdahi:
Hierarchical design space exploration for a class of digital systems.
- Pradip K. Jha, Nikil D. Dutt:
Rapid estimation for parameterized components in high-level synthesis.
- Subhrajit Bhattacharya, Franc Brglez, Sujit Dey:
Transformations and resynthesis for testability of RT-level control-data path specifications.
- Frank H. M. Franssen, Florin Balasa, Michaël F. X. B. van Swaaij, Francky Catthoor, Hugo De Man:
Modeling multidimensional data and control flow.
- Anthony J. Gadient, D. E. Thomas:
A dynamic approach to controlling high-level synthesis CAD tools.
- Daniel G. Saab:
Parallel-concurrent fault simulation.
- Amitava Majumdar, Sarma B. K. Vrudhula:
Analysis of signal probability in logic circuits using stochastic models.
- Hyunchul Shin, Chunghee Kim:
A simple yet effective technique for partitioning.
- Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
Analysis of resistive bridging fault detection in BiCMOS digital ICs.
Volume 1, Number 4, December 1993
Last update Fri May 24 20:59:05 2013
CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page
- Raghu Sastry, N. Ranganathan, Horst Bunke:
VLSI architectures for polygon recognition.
- Anna Antola, Alberto Avai, Luca Breveglieri:
Modular design methodologies for image processing architectures.
- Dinesh Somasekhar, V. Visvanathan:
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking.
- Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu:
Greedy hardware optimization for linear digital circuits using number splitting and refactorization.
- Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
ESPRESSO-SIGNATURE: a new exact minimizer for logic functions.
- Vinaya Kumar Singh, A. A. Diwan:
A heuristic for decomposition in multilevel logic optimization.
- W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana:
Faulty behavior of storage elements and its effects on sequential circuits.
- Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
Path delay fault simulation of sequential circuits.
- Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani:
Middle terminal cell models for efficient over-the-cell routing in high-performance circuits.
- Ed P. Huijbregts, Jochen A. G. Jess:
General gate array routing using a k-terminal net routing algorithm with failure prediction.
- K. S. V. Gopalarao, Purnendu K. Mozumder, Duane S. Boning:
An integrated technology CAD system for process and device designers.
- Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, W.-L. Yang:
The design and implementation of the Arithmetic Cube II, a VLSI signal processing system.
- Kaushik Roy, S. C. Prasad:
Circuit activity based logic synthesis for low power reliable operations.
- K. De, P. Banerjee:
PREST: a system for logic partitioning and resynthesis for testability.
- Dimitrios Kagaris, Spyros Tragoudas:
Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets.
- D. Das, Sharad C. Seth, Vishwani D. Agrawal:
Accurate computation of field reject ratio based on fault latency.
- D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan:
Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model.
- David C. Blight, Robert D. McLeod:
An adaptive message passing environment for water scale systems.
- R. Varadarajan, F. Augustine:
Efficient time-space mappings of nested loops onto multidimensional systolic arrays with a flexible buffer scheme.
- C. Bachelu, Martin Lefebvre:
A study of the use of local interconnect in CMOS leaf cell design.
- C. Ying, J. Gu:
Automated pin grid array package routing on multilayer ceramic substrates.