IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 1

Volume 1, Number 1, March 1993

• Pallab K. Chatterjee, G. B. Larrabee:
  Gigabit age microelectronics and their manufacture. 7-21
  
• Mario Kovac, N. Ranganathan, M. Varanasi:
  SIGMA: a VLSI systolic array implementation of a Galois field GF(2 ^m) based multiplication and division algorithm. 22-30
  
• Raja Venkateswaran, Pinaki Mazumder:
  Coprocessor design for multilayer surface-mounted PCB routing. 31-45
  
• Fadi J. Kurdahi, Champaka Ramachandran:
  Evaluating layout area tradeoffs for high level applications. 46-55
  
• Y. He, Ugur Çilingiroglu, Edgar Sánchez-Sinencio:
  A high-density and low-power charge-based Hamming network. 56-62
  
• Richard Burch, Farid N. Najm, Ping Yang, Timothy N. Trick:
  A Monte Carlo approach for power estimation. 63-71
  
• John A. Nestor:
  Visual register-transfer description of VLSI microarchitectures. 72-76
  
• H. Lin, Fabrizio Lombardi, M. Lu:
  On the optimal reconfiguration of multipipeline arrays in the presence of faulty processing and switching elements. 76-79
  

Volume 1, Number 2, June 1993

• C. Sul, Robert D. McLeod, Witold Pedrycz:
  Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays. 224-228
  
• S.-Y. Kuo, S.-C. Liang:
  Design and analysis of defect tolerant hierarchical sorting networks. 219-223
  
• T.-Y. Wuu, Sarma B. K. Vrudhula:
  A design of a fast and area efficient multi-input Muller C-element. 215-219
  
• Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya:
  MARVLE: a VLSI chip for data compression using tree-based codes. 203-214
  
• Keshab K. Parhi, Takao Nishitani:
  VLSI architectures for discrete wavelet transforms. 191-202
  
• A. Sharma, R. Jain:
  Estimating architectural resources and performance for high-level synthesis applications. 175-190
  
• Joseph Varghese, Michael Butts, Jon Batcheller:
  An efficient logic emulation system. 171-174
  
• Smaragda Konstantinidou:
  The selective extra stage butterfly. 167-171
  
• Philip E. Madrid, Brian Millar, Earl E. Swartzlander Jr.:
  Modified Booth algorithm for high radix fixed-point multiplication. 164-167
  
• C.-S. Li, Harald S. Stone, Y. Kwark, C. M. Olsen:
  Fully differential optical interconnections for high-speed digital systems. 151-163
  
• A. Chatterjee:
  Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums. 138-150
  
• Horng-Fei Jyu, Sharad Malik, Srinivas Devadas, Kurt Keutzer:
  Statistical timing analysis of combinational logic circuits. 126-137
  
• Jalil Fadavi-Ardekani:
  M×N Booth encoded multiplier generator using optimized Wallace trees. 120-125
  
• Chris J. Myers, Teresa H. Y. Meng:
  Synthesis of timed asynchronous circuits. 106-119
  
• Lishing Liu, Jih-Kwon Peir:
  Cache sampling by sets. 98-105
  
• Tom Chen, Glen Sunada:
  Design of a self-testing and self-repairing structure for highly hierarchical ultra-large capacity memory chips. 88-97
  

Volume 1, Number 3, September 1993

• Reinaldo A. Bergamaschi, Andreas Kuehlmann:
  A system for production use of high-level synthesis. 233-243
  
• J. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, Michael Payer, Michael Pilsl, S. Rumler, H. Soukup, Norbert Wehn, Peter Duzy:
  The Siemens high-level synthesis system CALLAS. 244-253
  
• Catherine H. Gebotys:
  Throughput optimized architectural synthesis. 254-261
  
• Ulrich Holtmann, Rolf Ernst:
  Experiments with low-level speculative computation based on multiple branch prediction. 262-267
  
• Dave Filo, David C. Ku, Claudionor José Nunes Coelho Jr., Giovanni De Micheli:
  Interface optimization for concurrent systems under timing constraints. 268-281
  
• D. Sreenivasa Rao, Fadi J. Kurdahi:
  Hierarchical design space exploration for a class of digital systems. 282-295
  
• Pradip K. Jha, Nikil D. Dutt:
  Rapid estimation for parameterized components in high-level synthesis. 296-303
  
• Subhrajit Bhattacharya, Franc Brglez, Sujit Dey:
  Transformations and resynthesis for testability of RT-level control-data path specifications. 304-318
  
• Frank H. M. Franssen, Florin Balasa, Michaël F. X. B. van Swaaij, Francky Catthoor, Hugo De Man:
  Modeling multidimensional data and control flow. 319-327
  
• Anthony J. Gadient, D. E. Thomas:
  A dynamic approach to controlling high-level synthesis CAD tools. 328-341
  
• Daniel G. Saab:
  Parallel-concurrent fault simulation. 356-364
  
• Amitava Majumdar, Sarma B. K. Vrudhula:
  Analysis of signal probability in logic circuits using stochastic models. 365-379
  
• Hyunchul Shin, Chunghee Kim:
  A simple yet effective technique for partitioning. 380-386
  
• Michele Favalli, Marcello Dalpasso, Piero Olivo, Bruno Riccò:
  Analysis of resistive bridging fault detection in BiCMOS digital ICs. 342-355
  

Volume 1, Number 4, December 1993

• Raghu Sastry, N. Ranganathan, Horst Bunke:
  VLSI architectures for polygon recognition. 398-407
  
• Anna Antola, Alberto Avai, Luca Breveglieri:
  Modular design methodologies for image processing architectures. 408-414
  
• Dinesh Somasekhar, V. Visvanathan:
  A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. 415-422
  
• Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu:
  Greedy hardware optimization for linear digital circuits using number splitting and refactorization. 423-431
  
• Patrick C. McGeer, Jagesh V. Sanghavi, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  ESPRESSO-SIGNATURE: a new exact minimizer for logic functions. 432-440
  
• Vinaya Kumar Singh, A. A. Diwan:
  A heuristic for decomposition in multilevel logic optimization. 441-445
  
• W. K. Al-Assadi, Yashwant K. Malaiya, Anura P. Jayasumana:
  Faulty behavior of storage elements and its effects on sequential circuits. 446-452
  
• Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal:
  Path delay fault simulation of sequential circuits. 453-461
  
• Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani:
  Middle terminal cell models for efficient over-the-cell routing in high-performance circuits. 462-472
  
• Ed P. Huijbregts, Jochen A. G. Jess:
  General gate array routing using a k-terminal net routing algorithm with failure prediction. 473-481
  
• K. S. V. Gopalarao, Purnendu K. Mozumder, Duane S. Boning:
  An integrated technology CAD system for process and device designers. 482-490
  
• Robert Michael Owens, Thomas P. Kelliher, Mary Jane Irwin, Mohan Vishwanath, Raminder Singh Bajwa, W.-L. Yang:
  The design and implementation of the Arithmetic Cube II, a VLSI signal processing system. 491-502
  
• Kaushik Roy, S. C. Prasad:
  Circuit activity based logic synthesis for low power reliable operations. 503-513
  
• K. De, P. Banerjee:
  PREST: a system for logic partitioning and resynthesis for testability. 514-525
  
• Dimitrios Kagaris, Spyros Tragoudas:
  Cost-effective LFSR synthesis for optimal pseudoexhaustive BIST test sets. 526-536
  
• D. Das, Sharad C. Seth, Vishwani D. Agrawal:
  Accurate computation of field reject ratio based on fault latency. 537-545
  
• D. D. Sharma, Fred J. Meyer, Dhiraj K. Pradhan:
  Yield optimization of modular and redundant multimegabit RAMs: a study of effectiveness of coding versus static redundancy using the center-satellite model. 546-558
  
• David C. Blight, Robert D. McLeod:
  An adaptive message passing environment for water scale systems. 559-562
  
• R. Varadarajan, F. Augustine:
  Efficient time-space mappings of nested loops onto multidimensional systolic arrays with a flexible buffer scheme. 562-566
  
• C. Bachelu, Martin Lefebvre:
  A study of the use of local interconnect in CMOS leaf cell design. 566-571
  
• C. Ying, J. Gu:
  Automated pin grid array package routing on multilayer ceramic substrates. 571-575
  

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