IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 10

Volume 10, Number 1, February 2002

• Mark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy:
  Leakage control with efficient use of transistor stacks in single threshold CMOS. 1-5
  
• A. Manzak, C. Chakrabarti:
  A low power scheduling scheme with resources operating at multiple voltages. 6-14
  
• You-Sung Chang, Chong-Min Kyung:
  Conforming block inversion for low power memory. 15-19
  
• Ahmed M. Shams, Tarek Darwish, Magdy A. Bayoumi:
  Performance analysis of low-power 1-bit CMOS full adder cells. 20-29
  
• Mehrdad Nourani, Christos A. Papachristou:
  False path exclusion in delay analysis of RTL structures. 30-43
  
• Ing-Jer Huang, Ping-Huei Xie:
  Application of instruction analysis/scheduling techniques to resource allocation of superscalar processors. 44-54
  
• Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali:
  Least-square estimation of average power in digital CMOS circuits. 55-58
  
• G. N. Hoyer, Gin Yee, Carl Sechen:
  Locally clocked pipelines and dynamic logic. 58-62
  

Volume 10, Number 2, April 2002

• Enrico Macii, Ingrid Verbauwhede:
  Guest editorial: low-power electronics and design. 69-70
  
• Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry:
  Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies. 71-78
  
• Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David Blaauw:
  Duet: an accurate leakage estimation and optimization tool for dual-V_t circuits. 79-90
  
• Fatih Hamzaoglu, Yibin Ye, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea R. Stan, Vivek De:
  Analysis of dual-V_T SRAM cells with full-swing single-ended bit line sensing for on-chip cache. 91-95
  
• Luca Benini, Luca Macchiarulo, Alberto Macii, Massimo Poncino:
  Layout-driven memory synthesis for embedded systems-on-chip. 96-105
  
• Eike Schmidt, Gerd von Cölln, Lars Kruse, Frans Theeuwen, Wolfgang Nebel:
  Memory power models for multilevel power estimation and optimization. 106-109
  
• Wei-Chung Cheng, Massoud Pedram:
  Power-optimal encoding for a DRAM address bus. 109-118
  
• Yung-Hsiang Lu, Luca Benini, Giovanni De Micheli:
  Power-aware operating systems for interactive systems. 119-134
  
• Amit Sinha, Alice Wang, Anantha Chandrakasan:
  Energy scalable system design. 135-145
  
• Naehyuck Chang, Kwanho Kim, Hyung Gyu Lee:
  Cycle-accurate energy measurement and characterization with a case study of the ARM7TDMI [microprocessors]. 146-154
  
• Erik Lauwers, Georges G. E. Gielen:
  Power estimation methods for analog circuits for architectural exploration of integrated systems. 155-162
  
• Chih-Wen Lu, Chung-Len Lee:
  A low-power high-speed class-AB buffer amplifier for flat-panel-display application. 163-168
  
• Carl James Debono, Franco Maloberti, Joseph Micallef:
  On the design of low-voltage, low-power CMOS analog multipliers for RF applications. 168-174
  
• Dirk Stroobandt:
  Guest editorial - system-level interconnect prediction. 175-176
  
• Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt:
  Toward better wireload models in the presence of obstacles. 177-189
  

Volume 10, Number 3, June 2002

• Karam S. Chatha, Ranga Vemuri:
  Hardware-software partitioning and pipelined scheduling of transformative applications. 193-208
  
• Katherine Compton, Zhiyuan Li, James Cooley, Stephen Knol, Scott Hauck:
  Configuration relocation and defragmentation for run-time reconfigurable computing. 209-220
  
• Yonghee Im, Kaushik Roy:
  O²ABA: a novel high-performance predictable circuit architecture for the deep submicron era. 221-229
  
• Anoop Iyer, Diana Marculescu:
  Microarchitecture-level power management. 230-239
  
• Byoung-Woon Kim, Chong-Min Kyung:
  Exploiting intellectual properties with imprecise design costs for system-on-chip synthesis. 240-252
  
• Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno:
  Cosimulation-based power estimation for system-on-chip design. 253-266
  
• Jin-Fu Li, Cheng-Wen Wu:
  Efficient FFT network testing and diagnosis schemes. 267-278
  
• Guido Masera, M. Mazza, Gianluca Piccinini, F. Viglione, Maurizio Zamboni:
  Architectural strategies for low-power VLSI turbo decoders. 279-285
  
• Yehia Massoud, Jacob K. White:
  Simulation and modeling of the effect of substrate conductivity on coupling inductance and circuit crosstalk. 286-291
  
• Khurram Muhammad, Kaushik Roy:
  Reduced computational redundancy implementation of DSP algorithms using computation sharing vector scaling. 292-300
  
• João Navarro Jr., Wilhelmus A. M. Van Noije:
  Extended TSPC structures with double input/output data throughput for gigahertz CMOS circuit design. 301-308
  
• Jatuchai Pangjun, Sachin S. Sapatnekar:
  Low-power clock distribution using multiple voltages and reduced swings. 309-318
  
• Mondira Deb Pant, Pankaj Pant, D. Scott Wills:
  On-chip decoupling capacitor optimization using architectural level prediction. 319-326
  
• Rolando Ramírez Ortiz, John P. Knight:
  Compatible cell connections for multifamily dynamic logic gates. 327-340
  
• Paul-Peter Sotiriadis, Anantha P. Chandrakasan:
  A bus energy model for deep submicron technology. 341-350
  
• Liqiong Wei, Rongtian Zhang, Kaushik Roy, Zhanping Chen, David B. Janes:
  Vertically integrated SOI circuits for low-power and high-performance applications. 351-362
  
• Jianwen Zhu, Daniel D. Gajski:
  An ultra-fast instruction set simulator. 363-373
  
• Fatih Kocan, Daniel G. Saab:
  Correction to "ATPG for combinational circuits on configurable hardware". 374-374
  

Volume 10, Number 4, August 2002

• Fadi J. Kurdahi:
  Guest editorial special issue on system synthesis. 377-378
  
• Dirk Ziegenbein, Kai Richter, Rolf Ernst, Lothar Thiele, Jürgen Teich:
  SPI - a system model for heterogeneously specified embedded systems. 379-389
  
• Catherine H. Gebotys:
  A network flow approach to memory bandwidth utilization in embedded DSP core processors. 390-398
  
• Juanjo Noguera, Rosa M. Badia:
  HW/SW codesign techniques for dynamically reconfigurable architectures. 399-415
  
• Tony Givargis, Frank Vahid, Jörg Henkel:
  System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip. 416-422
  
• Hyunuk Jung, Kangnyoung Lee, Soonhoi Ha:
  Efficient hardware controller synthesis for synchronous dataflow graph in system level design. 423-428
  
• Forrest Brewer, Steve Haynal:
  Symbolic NFA scheduling of a RISC microprocessor. 429-434
  
• Oscal T.-C. Chen, R. R.-B. Sheen, S. Wang:
  A low-power adder operating on effective dynamic data ranges. 435-453
  
• Jörg Henkel, Yanbing Li:
  Avalanche: an environment for design space exploration and optimization of low-power embedded systems. 454-468
  
• Alexandre Solomatnikov, Dinesh Somasekhar, Naran Sirisantana, Kaushik Roy:
  Skewed CMOS: noise-tolerant high-performance low-power static circuit family. 469-476
  
• L.-D. Van:
  A new 2-D systolic digital filter architecture without global broadcast. 477-486
  
• Kevin T. Tang, Eby G. Friedman:
  Simultaneous switching noise in on-chip CMOS power distribution networks. 487-493
  
• Zhong-Fang Jin, J.-J. Laurin, Yvon Savaria:
  A practical approach to model long MIS interconnects in VLSI circuits. 494-507
  
• Sumant Ramprasad, Ibrahim N. Hajj, Farid N. Najm:
  A technique for Improving dual-output domino logic. 508-511
  
• Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee:
  An efficient BIST method for distributed small buffers. 512-515
  
• Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man:
  A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors. 515-518
  

Volume 10, Number 5, October 2002

• Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino:
  Minimizing memory access energy in embedded systems by selective instruction compression. 521-531
  
• Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
  Noise constrained transistor sizing and power optimization for dual Vs_t domino logic. 532-541
  
• Gang Qu, Miodrag Potkonjak:
  Techniques for energy-efficient communication pipeline design. 542-549
  
• Philip Heng Wai Leong, Ivan K. H. Leung:
  A microcoded elliptic curve processor using FPGA technology. 550-559
  
• José C. Monteiro, Arlindo L. Oliveira:
  Implicit FSM decomposition applied to low-power design. 560-565
  
• Arkadiy Morgenshtein, Alexander Fish, Israel A. Wagner:
  Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits. 566-581
  
• A. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl:
  Electrical and optical clock distribution networks for gigascale microprocessors. 582-594
  
• Mauro Olivieri:
  Theoretical system-level limits of power dissipation reduction under a performance constraint in VLSI microprocessor design. 595-600
  
• Massoud Pedram, Qing Wu:
  Battery-powered digital CMOS design. 601-607
  
• Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo:
  VLSI circuits for low-power high-speed asynchronous addition. 608-613
  
• Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon:
  Low-power data forwarding for VLIW embedded architectures. 614-622
  
• R. Tessier, S. Jana:
  Incremental compilation for parallel logic verification systems. 623-636
  
• Liming Xiu, Zhihong You:
  A "flying-adder" architecture of frequency and phase synthesis with scalability. 637-649
  
• Chantal Ykman-Couvreur, J. Lambrecht, Diederik Verkest, Francky Catthoor, Bengt Svantesson, Ahmed Hemani, F. Wolf:
  Dynamic memory management methodology applied to embedded telecom network systems. 650-667
  
• Nur A. Touba:
  Circular BIST with state skipping. 668-672
  
• Dohyung Kim, Chan-Eun Rhee, Soonhoi Ha:
  Combined data-driven and event-driven scheduling technique for fast distributed cosimulation. 672-678
  

Volume 10, Number 6, December 2002

• Yehea I. Ismail, Byron Krauter:
  Guest editorial: special issue on on-chip inductance in high-speed integrated circuits. 683-684
  
• Yehea I. Ismail:
  On-chip inductance cons and pros. 685-694
  
• Gerard V. Kopcsay, Byron Krauter, David Widiger, Alina Deutsch, Barry J. Rubin, H. H. Smith:
  A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis. 695-711
  
• Michael W. Beattie, Lawrence T. Pileggi:
  On-chip induction modeling: basics and advanced methods. 712-729
  
• Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi:
  Inductance model and analysis methodology for high-speed on-chip interconnect. 730-745
  
• Haitian Hu, Sachin S. Sapatnekar:
  Efficient inductance extraction using circuit-aware techniques. 746-761
  
• Andrey V. Mezhiba, Eby G. Friedman:
  Inductive properties of high-performance power distribution grids. 762-776
  
• Christer Svensson:
  Electrical interconnects revitalized. 777-788
  
• Yehia Massoud, Steve S. Majors, Jamil Kawa, Tareq Bustami, Don MacMillen, Jacob K. White:
  Managing on-chip inductive effects. 789-798
  
• Yu Cao, Xuejue Huang, N. H. Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Dennis Sylvester, Chenming Hu:
  Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion. 799-805
  
• Massimo Alioto, Gaetano Palumbo:
  Analysis and comparison on full adder block in submicron technology. 806-823
  
• Stelian Alupoaei, Srinivas Katkoori:
  Net-based force-directed macrocell placement for wirelength optimization. 824-835
  
• Chunhong Chen, Jiang Zhao, Majid Ahmadi:
  Probability-based approach to rectilinear Steiner tree problems. 836-843
  
• D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
  A clock power model to evaluate impact of architectural and technology optimizations. 844-855
  
• Tony Givargis, Frank Vahid, Jörg Henkel:
  Instruction-based system-level power evaluation of system-on-a-chip peripheral cores. 856-863
  
• Ramesh Karri, Kaijie Wu:
  Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. 864-875
  
• Kamal S. Khouri, Niraj K. Jha:
  Leakage power analysis and reduction during behavioral synthesis. 876-885
  
• Jai-Ming Lin, Hsin-Lung Chen, Yao-Wen Chang:
  Arbitrarily shaped rectilinear module placement using the transitive closure graph representation. 886-901
  
• Zhongfeng Wang, Zhipei Chi, Keshab K. Parhi:
  Area-efficient high-speed decoding schemes for turbo decoders. 902-912
  
• Wai Chung, Timothy Lo, Manoj Sachdev:
  A comparative analysis of low-power low-voltage dual-edge-triggered flip-flops. 913-918
  
• Farzan Fallah, Pranav Ashar, Srinivas Devadas:
  Functional vector generation for sequential HDL models under an observability-based code coverage metric. 919-923
  
• Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau, Ren-Der Chen:
  Design of a dynamic pipelined architecture for fuzzy color correction. 924-929
  
• Rung-Bin Lin, Chi-Ming Tsai:
  Theoretical analysis of bus-invert coding. 929-934
  
• Peter Oehler, Christoph Grimm, Klaus Waldschmidt:
  A methodology for system-level synthesis of mixed-signal applications. 935-942
  
• Shanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn:
  ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuits. 942-949
  

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