Volume 12, Number 1, January 2004
, Ivan S. Kourtev
: Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits.
, Alexandre F. Tenca
: A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm.
Radu M. Secareanu
, Scott Warner
, Scott Seabridge
, Cathie Burke
, Juan Becerra
, Thomas E. Watrobski
, Christopher Morton
, William Staub
, Thomas Tellier
, Ivan S. Kourtev
, Eby G. Friedman
: Substrate coupling in digital circuits in mixed-signal smart-power systems.
Volume 12, Number 2, February 2004
, An-Yeu Wu
, Jyh-Ting Lai
: High-performance VLSI architecture of adaptive decision feedback equalizer based on predictive parallel branch slicer (PPBS) scheme.
Volume 12, Number 3, March 2004 International Symposium on Low-Power Electronics and Design
, Malay Haldar
, Anshuman Nayak
, Victor Kim
, Vikram Saxena
, Steven Parkes
, Debabrata Bagchi
, Satrajit Pal
, Nikhil Tripathi
, David Zaretsky
, R. Anderson
, J. R. Uribe
: Overview of a compiler for synthesizing MATLAB programs onto FPGAs.
Volume 12, Number 4, April 2004
International Workshop on System Level Interconnect Prediction (SLIP)
, Danny Crookes
: From application descriptions to hardware in seconds: a logic-based approach to bridging the gap.
Volume 12, Number 5, May 2004
Volume 12, Number 6, June 2004
, Wayne Wolf
: Reducing dynamic power consumption in synchronous sequential digital designs using retiming and supply voltage scaling.
, N. Bhat
: An offset compensation technique for latch type sense amplifiers in high-speed low-power SRAMs.
Volume 12, Number 7, July 2004
, Beomsup Kim
: Quadrature direct digital frequency synthesizers using interpolation-based angle rotation.
, Sujit Dey
, Li Chen
: Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses.
, Alex Orailoglu
: Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.
, Taewhan Kim
: Tight integration of timing-driven synthesis and placement of parallel multiplier circuits.
Volume 12, Number 8, August 2004
Volume 12, Number 9, September 2004
Volume 12, Number 10, October 2004
: Unifying mesh- and tree-based programmable interconnect.
Volume 12, Number 11, November 2004
: CAD for nanometer silicon design challenges and success.
, P. C.-Y. Wu
: Architectural design and analysis of learnable self-feedback ratio-memory cellular nonlinear network (SRMCNN) for nanoelectronic systems.
Gerald Esch Jr.
, Tom Chen
: Near-linear CMOS I/O driver with less sensitivity to process, voltage, and temperature variations.
Volume 12, Number 12, December 2004
, Michel S. Nakhla
: Efficient simulation of nonuniform transmission lines using integrated congruence transform.
: Sequence-switch coding for low-power data transmission.