Volume 2, Number 1, March 1994
- Daniel Audet, Yvon Savaria, N. Arel:
Pipelining communications in large VLSI/ULSI systems.
- Catherine H. Gebotys:
An optimization approach to the synthesis of multichip architectures.
- Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King:
MULTIPAR: behavioral partition for synthesizing multiprocessor architectures.
- Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson:
The yield enhancement of field-programmable gate arrays.
- Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, J. C. Curlander:
VLSI systolic binary tree-searched vector quantizer for image compression.
- Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel:
Block-oriented programmable design with switching network interconnect.
- J. Ghosh, A. Varma, N. Krishnamurthy:
Distributed control schemes for fast arbitration in large crossbar networks.
- Steve C.-Y. Huang, Wayne Wolf:
Performance-driven synthesis in controller-datapath systems.
- Lih-Gwo Jeng, Liang-Gee Chen:
Rate-optimal DSP synthesis by pipeline and minimum unfolding.
- Vojin G. Oklobdzija:
An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis.
- Sungho Kang, Stephen A. Szygenda:
The simulation automation system (SAS); concepts, implementation, and results.
- Brian S. Cherkauer, Eby G. Friedman:
Channel width tapering of serially connected MOSFET's with emphasis on power dissipation.
- Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang:
A Gaussian synapse circuit for analog VLSI neural networks.
Volume 2, Number 2, June 1994
- Jason Cong, Yuzheng Ding:
On area/depth trade-off in LUT-based FPGA technology mapping.
- Tassos Markas, Mark Royals, Nick Kanopoulos:
Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations.
- Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza:
ALADIN: a multilevel testability analyzer for VLSI system design.
- Andrew Seawright, Forrest Brewer:
Clairvoyant: a synthesis system for production-based specification.
- K. De, C. Natarajan, D. Nair, P. Banerjee:
RSYN: a system for automated synthesis of reliable multilevel circuits.
- S. C. Leung, Hon Fung Li:
A syntax-directed translation for the synthesis of delay-insensitive circuits.
- Minjoong Rim, Ashutosh Mujumdar, Rajiv Jain, Renato De Leone:
Optimal and heuristic algorithms for solving the binding problem.
- Lishing Liu:
Partial address directory for cache access.
- Marc E. Levitt, Kaushik Roy, Jacob A. Abraham:
BiCMOS logic testing.
- Israel Koren, Zahava Koren, Charles H. Stapper:
A statistical study of defect maps of large area VLSI IC's.
- Choong Gun Oh, Hee Yong Youn:
On concurrent error location and correction of FFT networks.
- Razak Hossain, Leszek D. Wronski, Alexander Albicki:
Low power design using double edge triggered flip-flops.
- Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia:
Algorithms and bounds for layer assignment of MCM routing.
Volume 2, Number 3, September 1994
- Panagiotis Tzionas, Panagiotis G. Tsalides, Adonios Thanailakis:
A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation.
- Chien-In Henry Chen, Joel T. Yuen:
Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design.
- Hong-Shin Jun, Sun-Young Hwang:
Design of a pipelined datapath synthesis system for digital signal processing.
- Alex Orailoglu, Ramesh Karri:
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.
- Ming-Bo Lin, A. Yavuz Oruç:
A fault-tolerant permutation network modulo arithmetic processor.
- Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj:
Logic design error diagnosis and correction.
- Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang:
Certified timing verification and the transition delay of a logic circuit.
- R. V. Pelletier, Robert D. McLeod:
Loop based design for wafer scale systems.
- Chang N. Zhang, J. H. Weston, Y.-F. Yan:
Determining objective functions in systolic array designs.
- K. Tsang, Belle W. Y. Wei:
A VLSI architecture for a real-time code book generator and encoder of a vector quantizer.
- Barry S. Fagin, C. Renard:
Field programmable gate arrays and floating point arithmetic.
- Jacob Savir, Srinivas Patil:
On broad-side delay test.
- Alexandre Yakovlev, A. Petrov, Luciano Lavagno:
A low latency asynchronous arbitration circuit.
- Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin:
Power-delay characteristics of CMOS adders.
Volume 2, Number 4, December 1994
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- Lars Skovby Nielsen, C. Niessen, Jens Sparsø, Kees van Berkel:
Low-power operation using self-timed circuits and adaptive scaling of the supply voltage.
- William C. Athas, Lars J. Svensson, Jefferey G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou:
Low-power digital systems based on adiabatic-switching principles.
- Jason Cong, Cheng-Kok Koh:
Simultaneous driver and wire sizing for performance and power optimization.
- Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou:
Precomputation-based sequential logic optimization for low power.
- Vivek Tiwari, Sharad Malik, Andrew Wolfe:
Power analysis of embedded software: a first step towards software power minimization.
- Farid N. Najm:
A survey of power estimation techniques in VLSI circuits.
- Samit Chaudhuri, Robert A. Walker, J. E. Mitchell:
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem.
- Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi:
A C-testable carry-free divider.
- Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz:
Fuzzy logic approach to VLSI placement.
- Kaushik Roy, Sudip Nag:
Automatic synthesis of FPGA channel architecture for routability and performance.
- Sandip Kundu:
Diagnosing scan chain faults.
- Charles E. Stroud:
Reliability of majority voting based VLSI fault-tolerant circuits.
- R. Katti:
A modified Booth algorithm for high radix fixed-point multiplication.
- Chaitali Chakrabarti, Li-Yu Wang:
Novel sorting network-based architectures for rank order filters.