VLSI Design, Volume 2012

Volume 2012, 2012

• S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha:
  Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm.
  
• Maxwell Walton, Omar Ahmed, Gary William Grewal, Shawki Areibi:
  An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.
  
• Roberta Piscitelli, Andy D. Pimentel:
  A Signature-Based Power Model for MPSoC on FPGA.
  
• Emanuele Cannella, Onur Derin, Paolo Meloni, Giuseppe Tuveri, Todor Stefanov:
  Adaptivity Support for MPSoCs Based on Process Migration in Polyhedral Process Networks.
  
• Shiwani Singh, Tripti Sharma, K. G. Sharma, B. P. Singh:
  9T Full Adder Design in Subthreshold Region.
  
• Zhen-dong Zhang, Bin Wu, Yu-mei Zhou, Xin Zhang:
  Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN.
  
• Yahya Jan, Lech Józwiak:
  Communication and Memory Architecture Design of Application-Specific High-End Multiprocessors.
  
• Paolo Meloni, Sebastiano Pomata, Giuseppe Tuveri, Simone Secchi, Luigi Raffo, Menno Lindwer:
  Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper.
  
• Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari:
  Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design.
  
• Christina Gimmler-Dumont, Frank Kienle, Bin Wu, Guido Masera:
  A System View on Iterative MIMO Detection: Dynamic Sphere Detection versus Fixed Effort List Detection.
  
• Joyjit Mukhopadhyay, Soumya Pandit:
  Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics.
  
• Muhammad Martuza, Khan A. Wahid:
  Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC-1, AVS, and HEVC.
  
• Guilherme Corrêa, Daniel Palomino, Cláudio Machado Diniz, Sergio Bampi, Luciano Volcan Agostini:
  Low-Complexity Hierarchical Mode Decision Algorithms Targeting VLSI Architecture Design for the H.264/AVC Video Encoder.
  
• P. Balasubramanian, David A. Edwards, W. B. Toms:
  Redundant Logic Insertion and Latency Reduction in Self-Timed Adders.
  
• Van Tam Nguyen, Frederic Villain, Yann Le Guillou:
  Cognitive Radio RF: Overview and Challenges.
  
• Logan M. Rakai, Amin Farshidi, Laleh Behjat, David T. Westwick:
  A New Length-Based Algebraic Multigrid Clustering Algorithm.
  
• Khaled Grati, Nadia Khouja, Bertrand Le Gal, Adel Ghazel:
  Power Consumption Models for Decimation FIR Filters in Multistandard Receivers.
  
• Massimo Bariani, Paolo Lambruschini, Marco Raggio:
  An Efficient Multi-Core SIMD Implementation for H.264/AVC Encoder.
  
• Philipp Schläfer, Christian Weis, Norbert Wehn, Matthias Alles:
  Design Space of Flexible Multigigabit LDPC Decoders.
  
• Maher Jridi, Alfalou FALOU Ayman, Pramod Kumar Meher:
  Optimized Architecture Using a Novel Subexpression Elimination on Loeffler Algorithm for DCT-Based Image Compression.
  
• Christos Ttofis, Theocharis Theocharides:
  Hardware Design Considerations for Edge-Accelerated Stereo Correspondence Algorithms.
  
• Muhammad Awais, Carlo Condo:
  Flexible LDPC Decoder Architectures.
  
• Dionysios Diamantopoulos, Kostas Siozios, Sotirios Xydis, Dimitrios Soudris:
  A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems.
  
• Ashfaq Ahmed, Muhammad Usman Shahid, Ata ur Rehman:
  Point DCT VLSI Architecture for Emerging HEVC Standard.
  
• Min Pan, Yue Xu, Yanheng Zhang, Chris Chu:
  FastRoute: An Efficient and High-Quality Global Router.
  
• Sergio Saponara, Luca Fanucci:
  Homogeneous and Heterogeneous MPSoC Architectures with Network-On-Chip Connectivity for Low-Power and Real-Time Multimedia Signal Processing.
  
• Khaled Jerbi, Mickaël Raulet, Olivier Déforges, Mohamed Abid:
  Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs.
  
• B. Bala Tripura Sundari:
  Design Space Exploration of Deeply Nested Loop 2D Filtering and 6 Level FSBM Algorithm Mapped onto Systolic Array.
  
• Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy:
  Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation.
  
• Maurizio Martina, Muhammad Shafique, Andrey Norkin:
  VLSI Circuits, Systems, and Architectures for Advanced Image and Video Compression Standards.
  
• Maher Assaad, Mohammed H. Alser:
  Design of an All-Digital Synchronized Frequency Multiplier Based on a Dual-Loop (D/FLL) Architecture.
  
• Leonardo Palacios-Luengas, Gonzalo Isaac Duchen-Sánchez, José Luis Aragon Aragón-Vera, Ruben Vázquez-Medina:
  Digital Noise Generator Design Using Inverted 1D Tent Chaotic Map.
  
• Xin Zhao, Chris Chu:
  Line Search-Based Inverse Lithography Technique for Mask Design.
  
• D. S. Harish Ram, M. C. Bhuvaneswari, Shanthi S. Prabhu:
  A Novel Framework for Applying Multiobjective GA and PSO Based Approaches for Simultaneous Area, Delay, and Power Optimization in High Level Synthesis of Datapaths.
  
• Sheng-Chieh Huang, Hui-Min Wang, Wei-Yu Chen:
  A ±6 ms-Accuracy, 0.68 mm², and 2.21 μW QRS Detection ASIC.
  
• Chia-Hao Fang, I.-tao Lung, Chih-Peng Fan:
  Absolute Difference and Low-Power Bus Encoding Method for LCD Digital Display Interfaces.
  
• Lilia Zaourar, Yann Kieffer, Chouki Aktouf:
  A Graph-Based Approach to Optimal Scan Chain Stitching Using RTL Design Descriptions.
  

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