The Journal of VLSI Signal Processing, Volume 10

Volume 10, Number 1, June 1995

• M. Yan, John V. McCanny, Y. Hu:
  VLSI architectures for vector quantization. 5-23
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• Randy S. Roberts, Herschel H. Loomis Jr.:
  Parallel computation structures for a class of cyclic spectral analysis algorithms. 25-40
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• Farhad Fuad Islam, Keikichi Tamaru:
  High speed merged array multiplication. 41-52
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• D. E. Metafas, Constantinos E. Goutis:
  A floating-point advanced cordic processor. 53-65
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• Chung-Yu Wu, Ron-Yi Liu:
  CMOS current-mode implementation of spatiotemporal probabilistic neural networks for speech recognition. 67-84
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• Cheng-Wen Wu, Ming-Kwang Chang:
  Bit-level systolic arrays for finite-field multiplications. 85-92
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• A. S. de la Vega, Paulo S. R. Diniz, Antônio C. Mesquita, Andreas Antoniou:
  A modular distributed-arithmetic implementation of the inner product and its application to digital filters. 93-106
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Volume 10, Number 2, July 1995

• Prashanth Kuchibhotla, Bhaskar D. Rao:
  A methodology for fast scheduling of partitioned systolic algorithms. 111-126
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• Mohammad Eshghi, Joanne DeGroat:
  A parallel binary structured LMS algorithm for transversal adaptive filters. 127-140
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• Francisco Argüello, Emilio L. Zapata:
  Constant geometry split-radix algorithms. 141-152
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• Giuseppe Caire, Javier Ventura-Traveset, M. Hollreiser, Ezio Biglieri:
  Systolic architecture for the VLSI implementation of high-speed staged decoders/quantizers. 153-168
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• Ling Chen, Henry Y. H. Chuang:
  Designing systolic architectures for complete Euclidean distance transform. 169-179
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• Jingling Xue:
  Closed-form mapping conditions for the synthesis of linear processor arrays. 181-199
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Volume 10, Number 3, October 1995

• Liang-Fang Chao, Edwin Hsing-Mean Sha:
  Static scheduling for synthesis of DSP algorithms on various models. 207-223
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• Henry Y. H. Chuang, Ling Chen:
  VLSI architecture for fast 2D discrete orthonormal wavelet transform. 225-236
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• Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri:
  Area efficient computing structures for concurrent error detection in systolic arrays. 237-260
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• Mark J. Bentum, Martin M. Samsom, Cornelis H. Slump:
  A multi-ASIC real-time implementation of the two dimensional affine transform with a bilinear interpolation scheme. 261-273
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• Liang-Gee Chen, Yeu-Shen Jehng, Tzi-Dar Chiueh:
  Pipeline interleaving design for FIR, IIR, and FFT array processors. 275-293
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• Lothar Thiele:
  Resource constrained scheduling of uniform algorithms. 295-310
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