Volume 11,
Numbers 1-2,
October 1995
- Magdy A. Bayoumi:
Introduction.
5-6
- Catherine H. Gebotys:
An optimal methodology for synthesis of DSP multichip architectures.
9-19
- Sati Banerjee, Paul M. Chau, Ronald D. Fellman:
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems.
21-34
- Hyeong-Kyo Kim, Thomas P. Barnwell:
A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs.
35-50
- Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner:
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.
51-74
- Ching-Yi Wang, Keshab K. Parhi:
Resource-constrained loop list scheduler for DSP algorithms.
75-96
- Marc Pauwels, Gert Goossens, Francky Catthoor, Hugo De Man:
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures.
97-112
- Yoav Yaacoby, Peter R. Cappello:
Converting affine recurrence equations to quasi-uniform recurrence equations.
113-131
- Yin-Tsung Hwang, Yu Hen Hu:
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays.
133-150
- Michael Ogbonna Esonu, Asim J. Al-Khalili, Salim Hariri, Dhamin Al-Khalili:
Design techniques for fault-tolerant systolic arrays.
151-168
- Nam Ling:
A special purpose formal verifier for systolic designs in DSP applications.
169-187
Volume 11,
Number 3,
December 1995
Copyright © Tue Dec 1 16:38:33 2009
by Michael Ley (ley@uni-trier.de)
