The Journal of VLSI Signal Processing, Volume 24

Volume 24, Number 1, February 2000

• Elias S. Manolakos, Wayne Burleson:
  Guest Editor's Introduction. 5-6
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• Paul D. Fiore:
  Efficient Wordlength Reduction Techniques for DSP Applications. 9-18
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• Shiro Kobayashi, Gerhard Fettweis:
  A Hierarchical Block-Floating-Point Arithmetic. 19-30
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• Richard P. Kleihorst, René J. van der Vleuten:
  DCT-Domain Embedded Memory Compression for Hybrid Video Coders. 31-41
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• Sangjin Hong, Wayne E. Stark:
  Design and Implementation of a Low Complexity VLSI Turbo-Code Decoder Architecture for Low Energy Mobile Wireless Communications. 43-57
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• Sydney Reader, Won Namgoong, Teresa H. Y. Meng:
  Partitioning Analog and Digital Processing in Mixed-Signal Systems. 59-65
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• Gaye Lightbody, Richard Walke, Roger Woods, John V. McCanny:
  Linear QR Architecture for a Single Chip Adaptive Beamformer. 67-81
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• Eckart Zitzler, Jürgen Teich, Shuvra S. Bhattacharyya:
  Multidimensional Exploration of Software Implementations for DSP Algorithms. 83-98
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• Andrew Stone, Elias S. Manolakos:
  DG2VHDL: A Tool to Facilitate the High Level Synthesis of Parallel Processing Array Architectures. 99-120
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Volume 24, Numbers 2-3, March 2000

• Jeffrey Arnold, Wayne Luk, Ken Pocek:
  Guest Editors' Introduction. 127
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• Herman Schmit, Srihari Cadambi, Matthew Moe, Seth Copen Goldstein:
  Pipeline Reconfigurable FPGAs. 129-146
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• Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves:
  Design and Implementation of the MorphoSys Reconfigurable Computing Processor. 147-164
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• Maya Gokhale, Janice M. Stone, Edson Gomersall:
  Co-Synthesis to a Hybrid RISC/FPGA Architecture. 165-180
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• Meenakshi Kaul, Ranga Vemuri:
  Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems. 181-209
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• Oskar Mencer, Luc Séméria, Martin Morf, Jean-Marc Delosme:
  Application of Reconfigurable CORDIC Architectures. 211-221
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• Panagiotis Stogiannos, Apostolos Dollas, Vassilios Digalakis:
  A Configurable Logic Based Architecture for Real-Time Continuous Speech Recognition Using Hidden Markov Models. 223-240
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• Hugo de Garis, Michael Korkin:
  The CAM-Brain Machine (CBM): Real Time Evolution and Update of a 75 Million Neuron FPGA-Based Artificial Brain. 241-262
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