The Journal of VLSI Signal Processing, Volume 28

Volume 28, Numbers 1-2, May 2001

• Wayne Burleson, Naresh R. Shanbhag:
  Guest Editorial: Reconfigurable Signal Processing Systems. 5-6
  
• Russell Tessier, Wayne Burleson:
  Reconfigurable Computing for Digital Signal Processing: A Survey. 7-27
  
• Peter Bellows, Brad L. Hutchings:
  Designing Run-Time Reconfigurable Systems with JHDL. 29-45
  
• Marlene Wan, Hui Zhang, George Varghese, Martin Benes, Arthur Abnous, Vandana Prabhu, Jan M. Rabaey:
  Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System. 47-61
  
• David R. Martinez, Tyler J. Moeller, Ken Teitelbaum:
  Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor. 63-83
  
• Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo:
  Quantitative Analysis of FPGA-based Database Searching. 85-96
  
• Jean-Paul Heron, Roger Woods, Sakir Sezer, Richard H. Turner:
  Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. 97-113
  
• Uwe Meyer-Bäse, Antonio García, Fred J. Taylor:
  Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. 115-128
  
• Dannie Lau, Aaron Schneider, Milos D. Ercegovac, John D. Villasenor:
  A FPGA-based Library for On-Line Signal Processing. 129-143
  

Volume 28, Number 3, July 2001

• Chien-Yu Chen, Zhong-Lan Yang, Tu-Chih Wang, Liang-Gee Chen:
  A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform. 151-163
  
• Marco Ferretti, Davide Rizzo:
  A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme. 165-185
  
• José Fridman, Elias S. Manolakos:
  Distributed Memory Parallel Architecture Based on Modular Linear Arrays for 2-D Separable Transforms Computation. 187-203
  
• Shen-Fu Hsiao, Jian-Ming Tseng:
  Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec. 205-220
  
• Edwin A. Hakkennes, Stamatis Vassiliadis:
  Multimedia Execution Hardware Accelerator. 221-234
  
• Ding-Ming Kwai, Behrooz Parhami:
  Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization. 235-243
  
• Gregory Doumenis, George E. Konstantoulakis, G. Korinthios, George Lykakis, Dionisios I. Reisis, G. Synnefakis:
  A Parallel VLSI Video/Communication Controller. 245-257
  
• Francesco Gregoretti, Roberto Passerone, Leonardo Maria Reyneri, Claudio Sansoè:
  A High Speed VLSI Architecture for Handwriting Recognition. 259-278