The Journal of VLSI Signal Processing, Volume 3

Volume 3, Numbers 1-2, June 1991

• Josef A. Nossek:
  Introduction. 5-6
  
• Alfred Fettweis, Gunnar Nitsche:
  Numerical integration of partial differential equations using principles of multidimensional wave digital filters. 7-24
  
• Leon O. Chua, L. Yang, K. R. Krieg:
  Signal processing using cellular neural networks. 25-51
  
• A. Lumsdaine, John L. Wyatt Jr., Ibrahim M. Elfadel:
  Nonlinear analog networks for image smoothing and segmentation. 53-68
  
• J. G. M. C. Whirter, D. S. Broomhead, T. J. Shepherd:
  A systolic array for nonlinear adaptive filtering and pattern recognition. 69-75
  
• Jürgen Teich, Lothar Thiele:
  Control generation in the design of processor arrays. 77-92
  
• Josef G. Krammer:
  A sorter-based architecture for a parallel implementation of communication intensive algorithms. 93-103
  
• Gerhard Fettweis, Heinrich Meyr:
  Feedforward architectures for parallel Viterbi decoding. 105-119
  
• Tobias G. Noll:
  Carry-save architectures for high-speed digital signal processing. 121-140
  

Volume 3, Number 3, September 1991

• S. Y. Kung:
  Editorial. 147
  
• Ed F. Deprettere:
  Introduction. 149
  
• S. F. Hsieh, K. J. Ray Liu, Kung Yao:
  Systolic implementations of up/down-dating cholesky factorization using vectorized Gram-Schmidt pseudo orthoganalization. 151-161
  
• Marc Moonen, Joos Vandewalle:
  A square root covariance algorithm for constrained recursive least squares estimation. 163-172
  
• Hervé Le Verge, Christophe Mauras, Patrice Quinton:
  The ALPHA language and its use for the design of systolic arrays. 173-182
  
• Michaël F. X. B. van Swaaij, Jan Rosseel, Francky Catthoor, Hugo De Man:
  Synthesis of ASIC regular arrays for real-time image processing systems. 183-192
  
• Ingrid Verbauwhede, Francky Catthoor, Joos Vandewalle, Hugo De Man:
  In-place memory management of algebraic algorithms on application specific ICs. 193-200
  
• Jaime H. Moreno, Miguel E. Figueroa, Tomás Lang:
  Linear pseudosystolic array for partitioned matrix algorithms. 201-214
  
• Çetin Kaya Koç, Ching Yu Hung:
  Bit-level systolic arrays for modular multiplication. 215-223
  
• Anna Antola, Mariagiovanna Sami, Donatella Sciuto:
  Testing and diagnosis ofFFT arrays. 225-236
  
• Christian Lengauer, Jingling Xue:
  A systolic array for pyramidal algorithms. 237-257
  

Volume 3, Number 4, October 1991

• Vojin G. Oklobdzija, Belle Wei:
  Introduction. 263
  
• Brian D. Lee, Vojin G. Oklobdzija:
  Improved CLA scheme with optimized delay. 265-274
  
• Xiaoping Huang, Belle W. Y. Wei, Honglu Chen, Yuhai H. Mao:
  High-performance VLSI multiplier with a new redundant binary coding. 283-291
  
• Eric M. Schwarz, Michael J. Flynn:
  Cost-efficient high-radix division. 293-305
  
• Paul K.-G. Tu, Milos D. Ercegovac:
  Gate array implementation of on-line algorithms for floating-point operations. 307-317
  
• Thanos Stouraitis, Alexander Skavantzos:
  Multiplication of complex numbers encoded as polynomials. 319-328
  
• Theodora A. Varvarigou, Vwani P. Roychowdhury, Thomas Kailath:
  New algorithms for reconfiguring VLSI/WSI arrays. 329-344
  
• Vibeke Libby:
  Use of window addressable memories for high speed geometrical analysis. 345-355