The Journal of VLSI Signal Processing, Volume 33

Volume 33, Numbers 1-2, January 2003

• Mohammad Ibrahim, Earl E. Swartzlander Jr.:
  Guest Editorial. 5
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• Marc Daumas, David W. Matula:
  Further Reducing the Redundancy of a Notation Over a Minimally Redundant Digit Set. 7-18
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• Jen-Chuan Chih, Sau-Gee Chen:
  Fast CORDIC Algorithm Based on a New Recoding Scheme for Rotation Angles and Variable Scale Factors. 19-29
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• Vincent Lefèvre, Jean-Michel Muller:
  On-the-Fly Range Reduction. 31-35
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• Mark G. Arnold, Thomas A. Bailey, John R. Cowles:
  Error Analysis of the Kmetz/Maenner Algorithm. 37-53
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• Javier D. Bruguera, Tomás Lang:
  Multilevel Reverse-Carry Addition: Single and Dual Adders. 55-74
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• Vasily G. Moshnyaga:
  Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits. 75-82
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• Dusan Suvakovic, C. Andre T. Salama:
  Energy Efficient Adiabatic Multiplier-Accumulator Design. 83-103
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• T. Sansaloni, Javier Valls, Keshab K. Parhi:
  Digit-Serial Complex-Number Multipliers on FPGAs. 105-115
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• Jen-Shiun Chiang, Min-Shiou Tsai:
  A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling. 117-124
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• Álvaro Vázquez, Elisardo Antelo:
  Implementation of the Exponential Function in a Floating-Point Unit. 125-145
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• Jiun-In Guo, Jui-Cheng Yen:
  An Efficient IDCT Processor Design for HDTV Applications. 147-155
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• Pol-Lin Tai, Chii-Tung Liu, Jia-Shung Wang:
  An Integrated Systolic Array Design for Video Compression. 157-169
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• Javier Ramírez, Antonio García, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz:
  Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic. 171-190
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• Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai:
  A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. 191-197
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• Massimo Panella, Giuseppe Martinelli:
  An RNS Architecture for Quasi-Chaotic Oscillators. 199-220
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Volume 33, Number 3, March 2003

• Francky Catthoor, Marc Moonen:
  Guest Editorial: Special Issue on Signal Processing Systems: Part I. 227
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• Tilman Glökler, Andreas Hoffmann, Heinrich Meyr:
  Methodical Low-Power ASIP Design Space Exploration. 229-246
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• Jae Sung Lee, Myung Hoon Sunwoo:
  Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT. 247-254
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• Quynh-Lien Nguyen-Phuc, Carolina Miro Sorolla:
  An MPEG-4 Renderer for High Quality Video Composition and Texture Mapping. 255-265
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• Roberto R. Osorio, Bart Vanhoof:
  High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. 267-275
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• Chuxiang Li, Jianhua Lu, Jun Gu, Ming L. Liou:
  Robust Digital Terrestrial TV Broadcasting System with Error-Resilient Schemes. 277-285
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• Jean Cardinal:
  Tree-Structured Multiple Description Coding. 287-294
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• Nam Ling, Nien-Tsu Wang:
  A Real-Time Video Decoder for Digital HDTV. 295-306
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• Bruno Bougard, Liesbet Van der Perre, F. Maessen, A. Giulietti, V. Derudder, Francky Catthoor:
  Memory Power Reduction for High-Speed Implementation of Turbo Codes. 307-316
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• Yun-Nan Chang:
  An Efficient In-Place VLSI Architecture for Viterbi Algorithm. 317-324
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• Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Colin D. Walter:
  Fast Fourier Transforms Using the Complex Logarithmic Number System. 325-335
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• Wei Liu, Stephan Weiss, Lajos Hanzo:
  A Novel Method for Partially Adaptive Broadband Beamforming. 337-344
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