The Journal of VLSI Signal Processing, Volume 40

Volume 40, Number 1, May 2005

• Michael J. Schulte, Shuvra S. Bhattacharyya, Robert Schreiber:
  Guest Editorial. 5-6
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• Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
  Solving Out-of-Order Communication in Kahn Process Networks. 7-18
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• Holger Blume, H. T. Feldkämper, Tobias G. Noll:
  Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. 19-34
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• Alain Darte, Guillaume Huard:
  New Complexity Results on Array Contraction and Related Problems. 35-55
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• Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan:
  VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance. 57-72
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• Jaffrey Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca:
  A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System. 73-84
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• Ruby B. Lee, A. Murat Fiskiran:
  PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing. 85-108
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• José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
  High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. 109-123
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• Neil Burgess:
  New Models of Prefix Adder Topologies. 125-141
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• Peter Kornerup:
  Reviewing 4-to-2 Adders for Multi-Operand Addition. 143-152
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Volume 40, Number 2, June 2005

• Fan Xu, Guichang Zhong, Alan N. Willson Jr.:
  Analysis and VLSI Realization of a Blind Beamforming Algorithm. 159-174
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• Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
  VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters. 175-188
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• Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés:
  FPGA Implementation of a Pipelined On-Line Backpropagation. 189-213
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• Jarno K. Tanskanen, Reiner Creutzburg, Jarkko Niittylahti:
  On Design of Parallel Memory Access Schemes for Video Coding. 215-237
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• Sangjin Hong, Shu-Shin Chin:
  Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications. 239-259
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• Albert Mo Kim Cheng, Rajat Agarwal:
  Reducing Encoder Bit-Rate Variation in MPEG Video. 261-271
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Volume 40, Number 3, July 2005

• Myung Hoon Sunwoo, Wonyong Sung:
  Guest Editorial. 279-280
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• Jung L. Lee, Myung H. Sunwoo:
  Implementation of a Wireless Multimedia DSP Chip for Mobile Applications. 281-287
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• Dong-Ik Ko, Shuvra S. Bhattacharyya:
  Modeling of Block-Based DSP Systems. 289-299
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• Wonyong Sung, Youngho Ahn, Eunjoo Hwang:
  VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers. 301-310
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• Finbarr O'Regan, Conor Heneghan:
  A Low Power Algorithm for Sparse System Identification using Cross-Correlation. 311-333
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• Mehboob Alam, Wael M. Badawy, Vassil S. Dimitrov, Graham A. Jullien:
  An Efficient Architecture for a Lifted 2D Biorthogonal DWT. 335-342
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• Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen:
  VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. 343-353
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• Tarek Darwish, Magdy Bayoumi:
  Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures. 355-369
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• Mohammad M. Mansour, Naresh R. Shanbhag:
  A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. 371-382
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• Marc Leeman, David Atienza, Geert Deconinck, Vincenzo De Florio, José M. Mendías, Chantal Ykman-Couvreur, Francky Catthoor, Rudy Lauwereins:
  Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications. 383-396
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