The Journal of VLSI Signal Processing, Volume 6

Volume 6, Number 1, June 1993

• Hans Peter Graf:
  Special issue on VLSI neural networks. 5
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• Yuzo Hirai:
  Recent VLSI neural networks in Japan. 7-18
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• Hans Peter Graf, Eduard Säckinger, Lawrence D. Jackel:
  Recent developments of electronic neural nets in North America. 19-31
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• Krste Asanovic, Nelson Morgan, John Wawrzynek:
  Using simulations of reduced precision arithmetic to design a neuro-microprocessor. 33-44
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• Ulrich Ramacher, Jörg Beichter, Nico Brüls:
  A general-purpose signal processor architecture for neurocomputing and preprocessing applications. 45-56
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• Ji-chien Lee, Bing J. Sheu, Rama Chellappa:
  A mixed-signal VLSI competitive neuroprocessor for video motion detection. 57-66
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• Marwan A. Jabri, Stephen Pickard, P. Leong, Y. Xie:
  Algorithmic and implementation issues in analog low power learning neural network chips. 67-76
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• Yu-jhih Wu, Michael D. Alston, Paul M. Chau:
  Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network. 77-84
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• Karl-Heinz Zimmermann, Tien-Chien Lee, Sun-Yuan Kung:
  On partitioning and fault tolerance issues for neural array processors. 85-94
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Volume 6, Number 2, August 1993

• Will Moore, Wayne Luk:
  Introduction. 99-100
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• Gordon J. Brebner:
  Configurable array logic circuits for computing network error detection codes. 101-117
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• Les Mintzer:
  FIR filters with field-programmable gate arrays. 119-127
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• Barry S. Fagin:
  Quantitative measurements of FPGA utility in special and general purpose processors. 129-137
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• Sean Monaghan:
  A gate-level reconfigurable Monte carlo processor. 139-153
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• Jouni Isoaho, Jari Pasanen, Olli Vainio, Hannu Tenhunen:
  DSP system integration and prototyping with FPGAS. 155-172
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• Erik Brunvand:
  Using FPGAs to implement self-timed systems. 173-190
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• Miriam Leeser, Richard Chapman, Mark Aagaard, Mark H. Linderman, Stephan Meier:
  High level synthesis and generating FPGAs with the BEDROC system. 191-214
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Volume 6, Number 3, December 1993

• Giulio Casagrande, Armando Chiari, Carla Golla, Salvatore Miceli:
  Vlsi programmable digital filter for video signal processing. 219-231
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• David M. Mandelbaum:
  A method for calculation of the square root using combinatorial logic. 233-242
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• Tom Chen, Li Zhu:
  An expandable column fft architecture using circuit switching networks. 243-257
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• Jenn-Dong Sun, Hari Krishna, K.-Y. Lin:
  A superfast algorithm for single-error correction in rrns and hardware implementation. 259-269
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• Shuvra S. Bhattacharyya, Edward A. Lee:
  Scheduling synchronous dataflow graphs for efficient looping. 271-288
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• Jos Huisken, A. Delaruelle, B. Egberts, P. Eeckhout, Jef L. van Meerbergen:
  Synthesis of synchronous communication hardware in a multiprocessor architecture. 289-299
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• Miriam Leeser:
  High level synthesis and generation FPGAs with the BEDROC system. 7
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