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Tor M. Aamodt
2010 – today
- 2013
[j7]Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt: Cache-Conscious Thread Scheduling for Massively Multithreaded Processors. IEEE Micro 33(3): 78-85 (2013)- [c22]Hadi Jooybar, Wilson W. L. Fung, Mike O'Connor, Joseph Devietti, Tor M. Aamodt: GPUDet: a deterministic GPU architecture. ASPLOS 2013: 1-12
- [c21]Vitaly Zakharenko, Tor M. Aamodt, Andreas Moshovos: Characterizing the performance benefits of fused CPU/GPU systems using FusionSim. DATE 2013: 685-688
- [c20]Inderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor, Tor M. Aamodt: Cache coherence for GPU architectures. HPCA 2013: 578-590
- 2012
- [j6]Wilson Wai Lun Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt: Kilo TM: Hardware Transactional Memory for GPU Architectures. IEEE Micro 32(3): 7-16 (2012)
- [j5]Xi E. Chen, Tor M. Aamodt: Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors. IEEE Trans. Computers 61(7): 913-927 (2012)
- [j4]Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang: Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. VLSI Syst. 20(11): 1997-2010 (2012)
- [c19]
- [c18]Tayler H. Hetherington, Timothy G. Rogers, Lisa Hsu, Mike O'Connor, Tor M. Aamodt: Characterizing and evaluating a key-value store application on heterogeneous CPU-GPU systems. ISPASS 2012: 88-98
- [c17]Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt: Cache-Conscious Wavefront Scheduling. MICRO 2012: 72-83
- 2011
- [j3]Xi E. Chen, Tor M. Aamodt: Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. TACO 8(3): 10 (2011)
- [c16]Wilson W. L. Fung, Tor M. Aamodt: Thread block compaction for efficient SIMT control flow. HPCA 2011: 25-36
- [c15]Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt: Hardware transactional memory for GPU architectures. MICRO 2011: 296-307
- 2010
- [c14]Ali Bakhoda, John Kim, Tor M. Aamodt: On-chip network design considerations for compute accelerators. PACT 2010: 535-536
- [c13]Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, Tor M. Aamodt: Visualizing complex dynamics in many-core accelerator architectures. ISPASS 2010: 164-174
- [c12]Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt: Accelerating trace computation in post-silicon debug. ISQED 2010: 244-249
- [c11]Ali Bakhoda, John Kim, Tor M. Aamodt: Throughput-Effective On-Chip Networks for Manycore Accelerators. MICRO 2010: 421-432
2000 – 2009
- 2009
- [j2]Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt: Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware. TACO 6(2) (2009)
- [c10]Xi E. Chen, Tor M. Aamodt: A first-order fine-grained multithreaded throughput model. HPCA 2009: 329-340
- [c9]Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt: Analyzing CUDA workloads using a detailed GPU simulator. ISPASS 2009: 163-174
- [c8]George L. Yuan, Ali Bakhoda, Tor M. Aamodt: Complexity effective memory access scheduling for many-core accelerator architectures. MICRO 2009: 34-44
- 2008
- [j1]Tor M. Aamodt, Paul Chow: Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. ACM Trans. Embedded Comput. Syst. 7(3) (2008)
- [c7]Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang: Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. PACT 2008: 52-61
- [c6]Xi E. Chen, Tor M. Aamodt: Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. MICRO 2008: 59-70
- 2007
- [c5]
- [c4]Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt: Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. MICRO 2007: 407-420
- 2004
- [c3]Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen: Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95
- 2003
- [c2]Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen: A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24
- 2000
- [c1]Tor M. Aamodt, Paul Chow: Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. CASES 2000: 128-137
Coauthor Index
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last updated on 2013-06-12 21:36 CEST by the dblp team