Jaume Abella

Leonidas Kosmidis, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla: A cache design for probabilistically analysable real-time systems. DATE 2013: 513-518

Leonidas Kosmidis, Charlie Curtsinger, Eduardo Quiñones, Jaume Abella, Emery D. Berger, Francisco J. Cazorla: Probabilistic timing analysis on conventional cache designs. DATE 2013: 603-606

Bojan Maric, Jaume Abella, Mateo Valero: Efficient cache architectures for reliable hybrid voltage operation using EDC codes. DATE 2013: 917-920

Liliana Cucu-Grosjean, Luca Santinelli, Michael Houston, Code Lo, Tullio Vardanega, Leonidas Kosmidis, Jaume Abella, Enrico Mezzetti, Eduardo Quiñones, Francisco J. Cazorla: Measurement-Based Probabilistic Timing Analysis for Multi-path Programs. ECRTS 2012: 91-101

Bojan Maric, Jaume Abella, Mateo Valero: ADAM: an efficient data management mechanism for hybrid high and ultra-low voltage operation caches. ACM Great Lakes Symposium on VLSI 2012: 245-250

Eduardo Quiñones, Jaume Abella, Francisco J. Cazorla, Mateo Valero: Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems. SIGBED Review 8(3): 32-35 (2011)

Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González: Implementing End-to-End Register Data-Flow Continuous Self-Test. IEEE Trans. Computers 60(8): 1194-1206 (2011)

Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González: Compiler Directed Issue Queue Energy Reduction. T. HiPEAC 4: 42-62 (2011)

Bojan Maric, Jaume Abella, Francisco J. Cazorla, Mateo Valero: Hybrid high-performance low-power and ultra-low energy reliable caches. Conf. Computing Frontiers 2011: 12

Javier Carretero, Jaume Abella, Xavier Vera, Pedro Chaparro: Control-Flow Recovery Validation Using Microarchitectural Invariants. DFT 2011: 209-216

Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Yanos Sazeides, Mateo Valero: RVC: a mechanism for time-analyzable real-time processors with faulty caches. HiPEAC 2011: 97-106

Javier Carretero, Xavier Vera, Jaume Abella, Tanausú Ramírez, Matteo Monchiero, Antonio González: Hardware/software-based diagnosis of load-store queues using expandable activity logs. HPCA 2011: 321-331

Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Mateo Valero, Yanos Sazeides: RVC-based time-predictable faulty caches for safety-critical systems. IOLTS 2011: 25-30

Jaume Abella, Francisco J. Cazorla, Eduardo Quiñones, Arnaud Grasset, Sami Yehia, Philippe Bonnot, Dimitris Gizopoulos, Riccardo Mariani, Guillem Bernat: Towards improved survivability in safety-critical systems. IOLTS 2011: 240-245

Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González: Design of complex circuits using the Via-Configurable transistor array regular layout fabric. SoCC 2011: 166-169

Jaume Abella, Xavier Vera: Electromigration for microarchitects. ACM Comput. Surv. 42(2) (2010)

Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella: Microarchitectural Online Testing for Failure Detection in Memory Order Buffers. IEEE Trans. Computers 59(5): 623-637 (2010)

Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera: The split register file. DATE 2010: 945-948

Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González: High-Performance low-vcc in-order core. HPCA 2010: 1-11

Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González: VCTA: A Via-Configurable Transistor Array regular fabric. VLSI-SoC 2010: 335-340

Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin: Exploring the limits of early register release: Exploiting compiler analysis. TACO 6(3) (2009)

Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin: Energy-efficient register caching with compiler assistance. TACO 6(4) (2009)

Xavier Vera, Jaume Abella, Javier Carretero, Antonio González: Selective replication: A lightweight technique for soft errors. ACM Trans. Comput. Syst. 27(4) (2009)

Xavier Vera, Jaume Abella, Javier Carretero, Pedro Chaparro, Antonio González: Online error detection and correction of erratic bits in register files. IOLTS 2009: 81-86

Javier Carretero, Pedro Chaparro, Xavier Vera, Jaume Abella, Antonio González: End-to-end register data-flow continuous self-test. ISCA 2009: 105-115

Jaume Abella, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González: Low Vccmin fault-tolerant cache with highly predictable performance. MICRO 2009: 111-121

Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz: Refueling: Preventing Wire Degradation due to Electromigration. IEEE Micro 28(6): 37-46 (2008)

Pedro Chaparro, Jaume Abella, Javier Carretero, Xavier Vera: Issue system protection mechanisms. ICCD 2008: 599-604

Jaume Abella, Pedro Chaparro, Xavier Vera, Javier Carretero, Antonio González: On-Line Failure Detection and Confinement in Caches. IOLTS 2008: 3-9

Joseph M. Selga, Agustín Zaballos, Jaume Abella, Guiomar Corral: Model for polling in noisy multihop systems with application to PLC and AMR. ISCC 2008: 664-669

Javier Carretero, Xavier Vera, Pedro Chaparro, Jaume Abella: On-line Failure Detection in Memory Order Buffers. ITC 2008: 1-10

Alex Vallejo, Agustín Zaballos, Jaume Abella, Joseph M. Selga, Carles Duz: Performance of a Policy-Based Management System in IPv6 Networks Using COPS-PR. ICN 2007: 37

Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González: Fuse: A Technique to Anticipate Failures due to Degradation in ALUs. IOLTS 2007: 15-22

Xavier Vera, Jaume Abella: Surviving to Errors in Multi-Core Environments. IOLTS 2007: 260

Jaume Abella, Xavier Vera, Antonio González: Penelope: The NBTI-Aware Processor. MICRO 2007: 85-96

Jaume Abella, Antonio González: Heterogeneous way-size cache. ICS 2006: 239-248

Guiomar Corral, Albert Fornells, Elisabet Golobardes, Jaume Abella: Cohesion Factors: Improving the Clustering Capabilities of Consensus. IDEAL 2006: 488-495

Jaume Abella, Antonio González: SAMIE-LSQ: set-associative multiple-instruction entry load/store queue. IPDPS 2006

Jaume Abella, Antonio González, Xavier Vera, Michael F. P. O'Boyle: IATAC: a smart predictor to turn-off L2 cache lines. TACO 2(1): 55-77 (2005)

Xavier Vera, Jaume Abella, Josep Llosa, Antonio González: An accurate cost model for guiding data locality transformations. ACM Trans. Program. Lang. Syst. 27(5): 946-987 (2005)

Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin: Compiler Directed Early Register Release. IEEE PACT 2005: 110-122

Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González: Variable-Based Multi-module Data Caches for Clustered VLIW Processors. IEEE PACT 2005: 207-217

Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González: Software Directed Issue Queue Power Reduction. HPCA 2005: 144-153

Jaume Abella, Antonio González: Inherently Workload-Balanced Clustered Microarchitecture. IPDPS 2005

Joan Ruiz, Alex Vallejo, Jaume Abella: IPv6 Conformance and Interoperability Testing. ISCC 2005: 83-88

Jaume Abella, Antonio González: Low-Complexity Distributed Issue Queue. HPCA 2004: 73-83

Jaume Abella, Ramon Canal, Antonio González: Power- and Complexity-Aware Issue Queue Designs. IEEE Micro 23(5): 50-58 (2003)

Xavier Vera, Jaume Abella, Antonio González, Josep Llosa: Optimizing Program Locality Through CMEs and GAs. IEEE PACT 2003: 68-78

Jaume Abella, Antonio González: Power-Aware Adaptive Issue Queue and Register File. HiPC 2003: 34-43

Jaume Abella, Antonio González: Power Efficient Data Cache Designs. ICCD 2003: 8-13

Jaume Abella, Antonio González: On Reducing Register Pressure and Energy in Multiple-Banked Register Files. ICCD 2003: 14-20

Jaume Abella, Antonio González, Josep Llosa, Xavier Vera: Near-Optimal Loop Tiling by Means of Cache Miss Equations and Genetic Algorithms. ICPP Workshops 2002: 568-580