Jacob A. Abraham

Byoungho Kim, Jacob A. Abraham: Capacitor-Coupled Built-Off Self-Test in Analog and Mixed-Signal Embedded Systems. IEEE Trans. on Circuits and Systems 60-II(5): 257-261 (2013)

Jaeyong Chung, Joonsung Park, Jacob A. Abraham: A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories. IEEE Trans. VLSI Syst. 21(2): 281-291 (2013)

Junyoung Park, Ameya Chaudhari, Jacob A. Abraham: Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor. DATE 2013: 254-257

Kihyuk Han, Joon-Sung Yang, Jacob A. Abraham: Dynamic Trace Signal Selection for Post-Silicon Validation. VLSI Design 2013: 302-307

Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham: Built-in Self Test of RF Subsystems with Integrated Detectors. J. Electronic Testing 28(5): 557-569 (2012)

Hyunjin Kim, Jacob A. Abraham: A Built-in Self-Test Scheme for Memory Interfaces Timing Test and Measurement. J. Electronic Testing 28(5): 585-597 (2012)

Sachin Dileep Dasnurkar, Jacob A. Abraham: Calibration Enabled Scalable Current Sensor Module for Quiescent Current Testing. J. Electronic Testing 28(5): 697-704 (2012)

Vinod Viswanath, Jacob A. Abraham: Automatic and Correct Register Transfer Level Annotations for Low Power Microprocessor Design. J. Low Power Electronics 8(4): 424-439 (2012)

Baker Mohammad, Jacob A. Abraham: A reduced voltage swing circuit using a single supply to enable lower voltage operation for SRAM-based memory. Microelectronics Journal 43(2): 110-118 (2012)

Jaeyong Chung, Jacob A. Abraham: Refactoring of Timing Graphs and Its Use in Capturing Topological Correlation in SSTA. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 485-496 (2012)

Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham: Path Criticality Computation in Parameterized Statistical Timing Analysis Using a Novel Operator. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 497-508 (2012)

Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham: Testability-Driven Statistical Path Selection. IEEE Trans. on CAD of Integrated Circuits and Systems 31(8): 1275-1287 (2012)

Jaeyong Chung, Jacob A. Abraham: On Computing Criticality in Refactored Timing Graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1935-1939 (2012)

Mohamad A. Zeidan, Gaurab Banerjee, Ranjit Gharpurey, Jacob A. Abraham: Phase-Aware Multitone Digital Signal Based Test for RF Receivers. IEEE Trans. on Circuits and Systems 59-I(9): 2097-2110 (2012)

Byoungho Kim, Jacob A. Abraham: Imbalance-Based Self-Test for High-Speed Mixed-Signal Embedded Systems. IEEE Trans. on Circuits and Systems 59-II(11): 785-789 (2012)

Hyunjin Kim, Jacob A. Abraham: On-chip source synchronous interface timing test scheme with calibration. DATE 2012: 1146-1149

Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham: Indirect method for random jitter measurement on SoCs using critical path characterization. European Test Symposium 2012: 1-6

Mahesh Prabhu, Jacob A. Abraham: Functional test generation for hard to detect stuck-at faults using RTL model checking. European Test Symposium 2012: 1-6

Shahrzad Mirkhani, Jacob A. Abraham, Toai Vo, Hong Shin Jun, Bill Eklow: FALCON: Rapid statistical fault coverage estimation for complex designs. ITC 2012: 1-10

Junyoung Park, H. Mert Ustun, Jacob A. Abraham: Run-time Prediction of the Optimal Performance Point in DVS-based Dynamic Thermal Management. VLSI Design 2012: 155-160

Hyunjin Kim, Jacob A. Abraham: A Built-In Self-Test scheme for DDR memory output timing test and measurement. VTS 2012: 7-12

Eun Jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham: An oscillation-based test structure for timing information extraction. VTS 2012: 74-79

Ji Hwan (Paul) Chun, Siew Mooi Lim, Shao Chee Ong, Jae Wook Lee, Jacob A. Abraham: Test of phase interpolators in high speed I/Os using a sliding window search. VTS 2012: 134-139

Junyoung Park, Jacob A. Abraham: An aging-aware flip-flop design based on accurate, run-time failure prediction. VTS 2012: 294-299

Joonsung Park, Hongjoong Shin, Jacob A. Abraham: Pseudorandom Test of Nonlinear Analog and Mixed-Signal Circuits Based on a Volterra Series Model. J. Electronic Testing 27(3): 321-334 (2011)

Kihyuk Han, Joonsung Park, Jae Wook Lee, Jaeyong Chung, Eonjo Byun, Cheol-Jong Woo, Sejang Oh, Jacob A. Abraham: Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. J. Electronic Testing 27(4): 429-439 (2011)

Ramtilak Vemu, Jacob A. Abraham: CEDA: Control-Flow Error Detection Using Assertions. IEEE Trans. Computers 60(9): 1233-1245 (2011)

Byoungho Kim, Jacob A. Abraham: Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. IEEE Trans. on Circuits and Systems 58-I(8): 1773-1784 (2011)

Byoungho Kim, Jacob A. Abraham: Transformer-Coupled Loopback Test for Differential Mixed-Signal Dynamic Specifications. IEEE T. Instrumentation and Measurement 60(6): 2014-2024 (2011)

Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham: System accuracy estimation of SRAM-based device authentication. ASP-DAC 2011: 37-42

Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham: Path criticality computation in parameterized statistical timing analysis. ASP-DAC 2011: 249-254

Tung-Yeh Wu, Shih-Hsin Hu, Jacob A. Abraham: Robust power gating reactivation by dynamic wakeup sequence throttling. ASP-DAC 2011: 615-620

Hyunjin Kim, Jacob A. Abraham: On-Chip Programmable Dual-Capture for Double Data Rate Interface Timing Test. Asian Test Symposium 2011: 15-20

Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham: Post-Silicon Timing Validation Method Using Path Delay Measurements. Asian Test Symposium 2011: 232-237

Jaeyong Chung, Jinjun Xiong, Vladimir Zolotov, Jacob A. Abraham: Testability driven statistical path selection. DAC 2011: 417-422

Junyoung Park, Jacob A. Abraham: A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems. ISLPED 2011: 391-396

Jacob A. Abraham: Tutorial: "Manufacturing test of systems-on-a-chip (SoCs)". SoCC 2011: 272

Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham: Efficient and product-representative timing model validation. VTS 2011: 90-95

Hongjoong Shin, Joonsung Park, Jacob A. Abraham: Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. J. Electronic Testing 26(1): 73-86 (2010)

Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham: On-Chip Delay Measurement Based Response Analysis for Timing Characterization. J. Electronic Testing 26(6): 599-619 (2010)

Ji Hwan (Paul) Chun, Jae Wook Lee, Jacob A. Abraham: A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection. ASP-DAC 2010: 312-317

Hyunjin Kim, Jacob A. Abraham: A Low Cost Built-In Self-Test Circuit for High-Speed Source Synchronous Memory Interfaces. Asian Test Symposium 2010: 123-128

Joonsung Park, Jae Wook Lee, Jaeyong Chung, Kihyuk Han, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh: At-speed Test of High-Speed DUT Using Built-Off Test Interface. Asian Test Symposium 2010: 269-274

Sachin Dileep Dasnurkar, Jacob A. Abraham: Calibration-enabled scalable built-in current sensor compatible with very low cost ATE. European Test Symposium 2010: 119-124

Hyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo: A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. European Test Symposium 2010: 145-150

Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham: A delay measurement method using a shrinking clock signal. ACM Great Lakes Symposium on VLSI 2010: 139-142

Joonsoo Kim, Joonsoo Lee, Jacob A. Abraham: Toward reliable SRAM-based device identification. ICCD 2010: 313-320

Jagdish Chandra Patra, Jacob A. Abraham, Pramod Kumar Meher, Goutam Chakraborty: An improved SOM-based visualization technique for DNA microarray data analysis. IJCNN 2010: 1-7

Sachin Dileep Dasnurkar, Jacob A. Abraham: Real-time dynamic hybrid BiST solution for Very-Low-Cost ATE production testing of A/D converters with controlled DPPM. ISQED 2010: 562-569

Shakeel S. Abdulla, Haewoon Nam, Earl E. Swartzlander Jr., Jacob A. Abraham: High speed recursion-free CORDIC architecture. SoCC 2010: 65-70

Tung-Yeh Wu, Sriram Sambamurthy, Jacob A. Abraham: Estimation of maximum application-level power supply noise. SoCC 2010: 213-218

Jaeyong Chung, Joonsung Park, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo: Reducing test time and area overhead of an embedded memory array built-in repair analyzer with optimal repair rate. VTS 2010: 33-38

Mohamad A. Zeidan, Aritra Banerjee, Ranjit Gharpurey, Jacob A. Abraham: Multitone digital signal based test for RF receivers. VTS 2010: 343-348

Rajeshwary Tayade, Jacob A. Abraham: Critical Path Selection for Delay Testing Considering Coupling Noise. J. Electronic Testing 25(4-5): 213-223 (2009)

Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham: Dedicated Rewriting: Automatic Verification of Low Power Transformations in Register Transfer Level. J. Low Power Electronics 5(3): 339-353 (2009)

Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham: A Random Jitter RMS Estimation Technique for BIST Applications. Asian Test Symposium 2009: 9-14

Joonsung Park, Jaeyong Chung, Jacob A. Abraham: LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits. Asian Test Symposium 2009: 373-378

Shih-Hsin Hu, Tung-Yeh Wu, Jacob A. Abraham: SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000. DFT 2009: 136-144

Kihyuk Han, Joonsung Park, Jae Wook Lee, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo, Sejang Oh: Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip. European Test Symposium 2009: 129-134

Rajeshwary Tayade, Jacob A. Abraham: Critical Path Selection for Delay Test Considering Coupling Noise. European Test Symposium 2009: 163-168

Jaeyong Chung, Jacob A. Abraham: A hierarchy of subgraphs underlying a timing graph and its use in capturing topological correlation in SSTA. ICCAD 2009: 321-327

Shakeel S. Abdulla, Haewoon Nam, Mark McDermot, Jacob A. Abraham: A high throughput FFT processor with no multipliers. ICCD 2009: 485-490

Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Chris Papachristou: Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS 2009: 129

Shih-Hsin Hu, Jacob A. Abraham: Error detection in 2-D Discrete Wavelet lifting transforms. IOLTS 2009: 170-175

Sachin Dileep Dasnurkar, Jacob A. Abraham: Hybrid BiST Solution for Analog to Digital Converters with Low-cost Automatic Test Equipment Compatibility. ISCAS 2009: 9-12

Tung-Yeh Wu, Samaneh Gharahi, Jacob A. Abraham: An Area Efficient On-chip Static IR Drop Detector/Evaluator. ISCAS 2009: 2009-2012

Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal: Characterization of sequential cells for constraint sensitivities. ISQED 2009: 74-79

Sriram Sambamurthy, Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham: Functionally valid gate-level peak power estimation for processors. ISQED 2009: 753-758

Vinod Viswanath, Shobha Vasudevan, Jacob A. Abraham: Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL. VLSI Design 2009: 77-82

Jaeyong Chung, Jacob A. Abraham: Recursive Path Selection for Delay Fault Testing. VTS 2009: 65-70

Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham: On-Line Calibration and Power Optimization of RF Systems Using a Built-In Detector. VTS 2009: 285-290

Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham, Jiajin Tu: Sequential equivalence checking between system level and RTL descriptions. Design Autom. for Emb. Sys. 12(4): 377-396 (2008)

Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka: Performance-Optimized Design for Parametric Reliability. J. Electronic Testing 24(1-3): 129-141 (2008)

Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu: Controllability of Static CMOS Circuits for Timing Characterization. J. Electronic Testing 24(5): 481-496 (2008)

Rajeshwary Tayade, Jacob A. Abraham: Small-delay defect detection in the presence of process variations. Microelectronics Journal 39(8): 1093-1100 (2008)

Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham: Analytical model for the impact of multiple input switching noise on timing. ASP-DAC 2008: 514-517

Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche: A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902

Jacob A. Abraham: Implications of Technology Trends on System Dependability. DATE 2008: 940

Rajeshwary Tayade, Jacob A. Abraham: Critical Path Selection for Delay Test Considering Coupling Noise. European Test Symposium 2008: 119-124

Qingqi Dou, Jacob A. Abraham: Jitter Decomposition in High-Speed Communication Systems. European Test Symposium 2008: 157-162

Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan: On efficient generation of instruction sequences to test for delay defects in a processor. ACM Great Lakes Symposium on VLSI 2008: 279-284

Baker Mohammad, Stephen Bijansky, Adnan Aziz, Jacob A. Abraham: Adaptive SRAM memory for low power and high yield. ICCD 2008: 176-181

Ramtilak Vemu, Jacob A. Abraham: Budget-Dependent Control-Flow Error Detection. IOLTS 2008: 73-78

Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham: Cache Design for Low Power and High Yield. ISQED 2008: 103-107

Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda: Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED 2008: 213-219

Rajeshwary Tayade, Jacob A. Abraham: On-chip Programmable Capture for Accurate Path Delay Test and Characterization. ITC 2008: 1-10

Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman Solovyev, Jacob A. Abraham: A timing methodology considering within-die clock skew variations. SoCC 2008: 351-356

Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri: A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. VLSI Design 2008: 521-526

Qingqi Dou, Jacob A. Abraham: Low-cost Test of Timing Mismatch Among Time-Interleaved A/D Converters in High-speed Communication Systems. VTS 2008: 3-8

Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham: Low Cost RF Receiver Parameter Measurement with On-Chip Amplitude Detectors. VTS 2008: 203-208

Byoungho Kim, Nash Khouzam, Jacob A. Abraham: Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits. VTS 2008: 293-298

Joonsung Park, Hongjoong Shin, Jacob A. Abraham: Parallel Loopback Test of Mixed-Signal Circuits. VTS 2008: 309-316

Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham: Predicting mixed-signal dynamic performance using optimised signature-based alternate test. IET Computers & Digital Techniques 1(3): 159-169 (2007)

Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham: Improved verification of hardware designs through antecedent conditioned slicing. STTT 9(1): 89-101 (2007)

Shobha Vasudevan, Vinod Viswanath, Robert W. Sumners, Jacob A. Abraham: Automatic Verification of Arithmetic Circuits in RTL Using Stepwise Refinement of Term Rewriting Systems. IEEE Trans. Computers 56(10): 1401-1414 (2007)

Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Daniel G. Saab: Automatic Generation of Instructions to Robustly Test Delay Defects in Processors. European Test Symposium 2007: 173-178

Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham: Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI 2007: 61-66

Jen-Chieh Ou, Daniel G. Saab, Qiang Qiang, Jacob A. Abraham: Reducing verification overhead with RTL slicing. ACM Great Lakes Symposium on VLSI 2007: 399-404

Chaoming Zhang, Ranjit Gharpurey, Jacob A. Abraham: Built-In Test of RF Mixers Using RF Amplitude Detectors. ISQED 2007: 404-409

Joonsung Park, Hongjoong Shin, Jacob A. Abraham: Pseudorandom Test for Nonlinear Circuits Based on a Simplified Volterra Series Model. ISQED 2007: 495-500

Rajeshwary Tayade, Savithri Sundareswaran, Jacob A. Abraham: Small-Delay Defect Detection in the Presence of Process Variations. ISQED 2007: 711-716

Ramtilak Vemu, Sankar Gurumurthy, Jacob A. Abraham: ACCE: Automatic correction of control-flow errors. ITC 2007: 1-10

Jacob A. Abraham, Daniel G. Saab: Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. VLSI Design 2007: 6

Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham: Efficient Microprocessor Verification using Antecedent Conditioned Slicing. VLSI Design 2007: 43-49

Byoungho Kim, Zhenhai Fu, Jacob A. Abraham: Transformer-Coupled Loopback Test for Differential Mixed-Signal Specifications. VTS 2007: 291-296

Qingqi Dou, Jacob A. Abraham: Jitter decomposition in ring oscillators. ASP-DAC 2006: 285-290

Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt Jr.: Automatic insertion of low power annotations in RTL for pipelined microprocessors. DATE 2006: 496-501

Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka: Adaptive Design for Performance-Optimized Robustness. DFT 2006: 3-11

Byoungho Kim, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham: Optimized Signature-Based Statistical Alternate Test for Mixed-Signal Performance Parameters. European Test Symposium 2006: 199-204

Vivekananda M. Ve. Andersen, Jacob A. Abraham: Taming the Complexity of STE-based Design Verification Using Program Slicing. HLDVT 2006: 137-142

Ramtilak Vemu, Jacob A. Abraham: CEDA: Control-flow Error Detection through Assertions. IOLTS 2006: 151-158

Qingqi Dou, Jacob A. Abraham: Jitter Decomposition by Time Lag Correlation. ISQED 2006: 525-530

Sankar Gurumurthy, Shobha Vasudevan, Jacob A. Abraham: Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor. ITC 2006: 1-9

Jen-Chieh Ou, Daniel G. Saab, Jacob A. Abraham: HDL Program Slicing to Reduce Bounded Model Checking Search Overhead. ITC 2006: 1-7

Hongjoong Shin, Joonsung Park, Jacob A. Abraham: Built-in Fault Diagnosis for Tunable Analog Systems Using an Ensemble Method. ITC 2006: 1-10

Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu: Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. MEMOCODE 2006: 71-80

Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri: Delay Constrained Register Transfer Level Dynamic Power Estimation. PATMOS 2006: 36-46

Baker Mohammad, Paul Bassett, Jacob A. Abraham, Adnan Aziz: Cache Organization for Embeded Processors: CAM-vs-SRAM. SoCC 2006: 299-302

Qiang Qiang, Daniel G. Saab, Jacob A. Abraham: Checking Nested Properties Using Bounded Model Checking and Sequential ATPG. VLSI Design 2006: 225-230

Ramyanshu Datta, Gary D. Carpenter, Kevin J. Nowka, Jacob A. Abraham: A Scheme for On-Chip Timing Characterization. VTS 2006: 24-29

Hongjoong Shin, Byoungho Kim, Jacob A. Abraham: Spectral Prediction for Specification-Based Loopback Test of Embedded Mixed-Signal Circuits. VTS 2006: 412-419

Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham: Efficient Model Checking of Hardware Using Conditioned Slicing. Electr. Notes Theor. Comput. Sci. 128(6): 279-294 (2005)

Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham: A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor. Formal Methods in System Design 27(1-2): 67-112 (2005)

Qiang Qiang, Daniel G. Saab, Jacob A. Abraham: An Emulation Model for Sequential ATPG-Based Bounded Model Checking. FPL 2005: 469-474

Qiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham: Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP Core. ICCD 2005: 461-463

Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham: Testing and debugging delay faults in dynamic circuits. ITC 2005: 10

S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham: Automated mapping of pre-computed module-level test sequences to processor instructions. ITC 2005: 10

Jeongjin Roh, Jacob A. Abraham: Subband filtering for time and frequency analysis of mixed-signal circuit testing. IEEE T. Instrumentation and Measurement 53(2): 602-611 (2004)

Jianhua Gan, Shouli Yan, Jacob A. Abraham: Effects of noise and nonlinearity on the calibration of a non-binary capacitor array in a successive approximation analog-to-digital converter. ASP-DAC 2004: 292-297

Ramyanshu Datta, Antony Sebastine, Ashwin Raghunathan, Jacob A. Abraham: On-chip delay measurement for silicon debug. ACM Great Lakes Symposium on VLSI 2004: 145-148

Hongjoong Shin, Hak-soo Yu, Jacob A. Abraham: LFSR-based BIST for analog circuits using slope detection. ACM Great Lakes Symposium on VLSI 2004: 316-321

Ji Hwan (Paul) Chun, Hak-soo Yu, Jacob A. Abraham: An efficient linearity test for on-chip high speed ADC and DAC using loop-back. ACM Great Lakes Symposium on VLSI 2004: 328-331

Shobha Vasudevan, Jacob A. Abraham: Static program transformations for efficient software model checking. IFIP Congress Topical Sessions 2004: 257-282

Ramyanshu Datta, Jacob A. Abraham, Robert K. Montoye, Wendy Belluomini, Hung C. Ngo, Chandler McDowell, Jente B. Kuang, Kevin J. Nowka: A low latency and low power dynamic Carry Save Adder. ISCAS (2) 2004: 477-480

Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC 2004: 31-37

Ashwin Raghunathan, Ji Hwan (Paul) Chun, Jacob A. Abraham, Abhijit Chatterjee: Quasi-Oscillation Based Test for Improved Prediction of Analog Performance Parameters. ITC 2004: 252-261

Alper Sen, Vijay K. Garg, Jacob A. Abraham, Jayanta Bhadra: Formal Verification of a System-on-Chip Using Computation Slicing. ITC 2004: 810-819

Ramyanshu Datta, Ravi Gupta, Antony Sebastine, Jacob A. Abraham, Manuel A. d'Abreu: Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing. ITC 2004: 1118-1127

Hak-soo Yu, Hongjoong Shin, Ji Hwan (Paul) Chun, Jacob A. Abraham: Performance Characterization of Mixed-Signal Circuits Using a Ternary Signal Representation. ITC 2004: 1389-1397

Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV 2004: 103-109

Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115-

Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham: Program Slicing for ATPG-Based Property Checking. VLSI Design 2004: 591-596

Ashwin Raghunathan, Hongjoong Shin, Jacob A. Abraham, Abhijit Chatterjee: Prediction of Analog Performance Parameters Using Oscillation Based Test. VTS 2004: 377-382

Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri: A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages. J. Electronic Testing 19(2): 149-160 (2003)

Jeongjin Roh, Jacob A. Abraham: A comprehensive signature analysis scheme for oscillation-test. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1409-1423 (2003)

Sungbae Hwang, Jacob A. Abraham: Test data compression and test time reduction using an embedded microprocessor. IEEE Trans. VLSI Syst. 11(5): 853-862 (2003)

Hak-soo Yu, Jacob A. Abraham, Sungbae Hwang, Jeongjin Roh: Efficient loop-back testing of on-chip ADCs and DACs. ASP-DAC 2003: 651-656

Whitney J. Townsend, Jacob A. Abraham, Earl E. Swartzlander Jr.: Quadruple Time Redundancy Adders. DFT 2003: 250-256

Jianhua Gan, Shouli Yan, Jacob A. Abraham: Design and modeling of a 16-bit 1.5MSPS successive approximation ADC with non-binary capacitor array. ACM Great Lakes Symposium on VLSI 2003: 161-164

Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala: On-Line Error Detecting Constant Delay Adder. IOLTS 2003: 17-

Arun Krishnamachary, Jacob A. Abraham: Effects of Multi-cycle Sensitization on Delay Tests. VLSI Design 2003: 137-142

Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula: Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines. VLSI Design 2003: 243-248

Hak-soo Yu, Sungbae Hwang, Jacob A. Abraham: DSP-Based Statistical Self Test of On-Chip Converters. VTS 2003: 83-88

Kyoil Kim, Jacob A. Abraham, Jayanta Bhadra: Model Checking of Security Protocols with Pre-configuration. WISA 2003: 1-15

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita: Efficient Combinational Verification Using Overlapping Local BDDs and a Hash Table. Formal Methods in System Design 21(1): 95-101 (2002)

Jason Baumgartner, Andreas Kuehlmann, Jacob A. Abraham: Property Checking via Structural Analysis. CAV 2002: 151-165

Jing Zeng, Magdy S. Abadir, Jacob A. Abraham: False timing path identification using ATPG techniques and delay-based information. DAC 2002: 562-565

Vivekananda M. Vedula, Jacob A. Abraham: FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis. DATE 2002: 730-734

Jacob A. Abraham, Arun Krishnamachary, Raghuram S. Tupuri: A Comprehensive Fault Model for Deep Submicron Digital Circuits. DELTA 2002: 360-364

Daniel G. Saab, Fatih Kocan, Jacob A. Abraham: Massively Parallel/Reconfigurable Emulation Model for the D-algorithm. FPL 2002: 1172-1176

Arun Krishnamachary, Jacob A. Abraham: Test generation for resistive opens in CMOS. ACM Great Lakes Symposium on VLSI 2002: 65-70

Sungbae Hwang, Jacob A. Abraham: Selective-run built-in self-test using an embedded processor. ACM Great Lakes Symposium on VLSI 2002: 124-129

Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham: Native Mode Functional Self-Test Generation for Systems-on-Chip. ISQED 2002: 280-285

Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab: Verifying Properties Using Sequential ATPG. ITC 2002: 194-202

Sungbae Hwang, Jacob A. Abraham: Optimal BIST Using an Embedded Microprocessor. ITC 2002: 736-745

Hak-soo Yu, Jacob A. Abraham: An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. VLSI Design 2002: 441-446

Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra: Program Slicing for Hierarchical Test Generation. VTS 2002: 237-246

Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280

Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham: Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Design & Test of Computers 18(4): 26-35 (2001)

Suresh Seshadri, Jacob A. Abraham: Frequency Response Verification of Analog Circuits Using Global Optimization Techniques. J. Electronic Testing 17(5): 395-408 (2001)

Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: Using Abstract Specifications to Verify PowerPC^TM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402

Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham: Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519

Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: A language formalism for verification of PowerPC^TM custom memories using compositions of abstract specifications. HLDVT 2001: 134-141

Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri: Timing Verification and Delay Test Generation for Hierarchical Designs. VLSI Design 2001: 157-162

Henry Chang, Steve Dollens, Gordon Roberts, Charles E. Stroud, Mani Soma, Jacob A. Abraham: Analog and Mixed Signal Benchmark Circuit Development: Who Needs Them? VTS 2001: 415-416

Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validating PowerPC Microprocessor Custom Memories. IEEE Design & Test of Computers 17(4): 61-76 (2000)

Jian Shen, Jacob A. Abraham: An RTL Abstraction Technique for Processor Microarchitecture Validation and Test Generation. J. Electronic Testing 16(1-2): 67-81 (2000)

Nina Saxena, Jacob A. Abraham, Avijit Saha: Causality based generation of directed test cases. ASP-DAC 2000: 503-508

Vivekananda M. Vedula, Jacob A. Abraham: A novel methodology for hierarchical test generation using functional constraint composition. HLDVT 2000: 9-14

Jeongjin Roh, Suresh Seshadri, Jacob A. Abraham: Verification of Delta-Sigma Converters Using Adaptive Regression Modeling. ICCAD 2000: 182-187

Hak-soo Yu, Songjun Lee, Jacob A. Abraham: An Adder Using Charge Sharing and its Application in DRAMs. ICCD 2000: 311-317

Pradip Bose, Jacob A. Abraham: Performance and Functional Verification of Microprocessors. VLSI Design 2000: 58-63

Raghuram S. Tupuri, Jacob A. Abraham, Daniel G. Saab: Hierarchical Test Generation for Systems On a Chip. VLSI Design 2000: 198-

Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Automatic Validation Test Generation Using Extracted Control Models. VLSI Design 2000: 312-

Jeongjin Roh, Jacob A. Abraham: A Mixed-Signal BIST Scheme with Time-Division Multiplexing (TDM) Comparator and Counters. VLSI Design 2000: 572-

Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. VTS 2000: 9-14

Jeongjin Roh, Jacob A. Abraham: A Comprehensive TDM Comparator Scheme for Effective Analysis of Oscillation-Based Test. VTS 2000: 143-148

Dinos Moundanos, Jacob A. Abraham: On Design Validation Using Verification Technology. J. Electronic Testing 15(1-2): 173-189 (1999)

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An efficient filter-based approach for combinational verification. IEEE Trans. on CAD of Integrated Circuits and Systems 18(11): 1542-1557 (1999)

Zeyad Alkhalifa, V. S. S. Nair, Narayanan Krishnamurthy, Jacob A. Abraham: Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection. IEEE Trans. Parallel Distrib. Syst. 10(6): 627-641 (1999)

Jian Shen, Jacob A. Abraham, Dave Baker, Tony Hurson, Martin Kinkade, Gregorio Gervasio, Chen-chau Chu, Guanghui Hu: Functional Verification of the Equator MAP1000 Microprocessor. DAC 1999: 169-174

Raghuram S. Tupuri, Arun Krishnamachary, Jacob A. Abraham: Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor. DAC 1999: 647-652

Richard Raimi, Jacob A. Abraham: Detecting False Timing Paths: Experiments on PowerPC Microprocessors. DAC 1999: 737-741

Rajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: An Efficient Filter-Based Approach for Combinational Verification. DATE 1999: 132-137

Chia-Pin R. Liu, Jacob A. Abraham: Transistor Level Synthesis for Static CMOS Combinational Circuits. Great Lakes Symposium on VLSI 1999: 172-175

Dinos Moundanos, Jacob A. Abraham: Formal Checking of Properties in Complex Systems Using Abstractions. Great Lakes Symposium on VLSI 1999: 280-283

Robert W. Sumners, Jayanta Bhadra, Jacob A. Abraham: Improving Witness Search Using Orders on States. ICCD 1999: 452-457

Jeongjin Roh, Jacob A. Abraham: Subband filtering scheme for analog and mixed-signal circuit testing. ITC 1999: 221-229

Kyung Tek Lee, Jacob A. Abraham: Critical path identification and delay tests of dynamic circuits. ITC 1999: 421-430

Jacob A. Abraham: Position Statement: Increasing Test Coverage in a VLSI Design Course. ITC 1999: 1132

Rathish Jayabharathi, Manuel A. d'Abreu, Jacob A. Abraham: FzCRITIC - A Functional Timing Verifier Using a Novel Fuzzy Delay Model. VLSI Design 1999: 232-235

Jian Shen, Jacob A. Abraham: Verification of Processor Microarchitectures. VTS 1999: 189-194

Jian Shen, Jacob A. Abraham: Synthesis of Native Mode Self-Test Programs. J. Electronic Testing 13(2): 137-148 (1998)

Craig M. Chase, Prakash Arunachalam, Jacob A. Abraham: Memory Distribution: Techniques and Practice for CAD Applications. Parallel Computing 24(11): 1597-1615 (1998)

Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote: Abstraction Techniques for Validation Coverage Analysis and Test Generation. IEEE Trans. Computers 47(1): 2-14 (1998)

Naveena Nagi, Abhijit Chatterjee, Heebyung Yoon, Jacob A. Abraham: Signature analysis for analog and mixed-signal circuit test response compaction. IEEE Trans. on CAD of Integrated Circuits and Systems 17(6): 540-546 (1998)

Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell: From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS 1998: 296-301

Sujit Dey, Jacob A. Abraham, Yervant Zorian: High-level design validation and test. ICCAD 1998: 3

Nina Saxena, Jason Baumgartner, Avijit Saha, Jacob A. Abraham: To model check or not to model check. ICCD 1998: 314-320

Jian Shen, Jacob A. Abraham: Native mode functional test generation for processors with applications to self test and design validation. ITC 1998: 990-999

Kyung Tek Lee, Clay Nordquist, Jacob A. Abraham: Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits. VTS 1998: 34-41

Dinos Moundanos, Jacob A. Abraham: Using Verification Technology for Validation Coverage Analysis and Test Generation. VTS 1998: 254-259

Hoon Chang, Jacob A. Abraham: An Efficient Critical Path Tracing Algorithm for Designing High Performance Vlsi Systems. J. Electronic Testing 11(2): 119-129 (1997)

Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46(11): 1230-1245 (1997)

Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos: Automatic verification of implementations of large circuits against HDL specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 16(3): 217-228 (1997)

Jun Yuan, Jian Shen, Jacob A. Abraham, Adnan Aziz: On Combining Formal and Informal Verification. CAV 1997: 376-387

Robert W. Sumners, Jacob A. Abraham: Hierarchical Specification of System Behavior. HASE 1997: 134-140

Raghuram S. Tupuri, Jacob A. Abraham: A Novel Functional Test Generation Method for Processors Using Commercial ATPG. ITC 1997: 743-752

Raghuram S. Tupuri, Jacob A. Abraham: A Novel Hierarchical Test Generation Method for Processors. VLSI Design 1997: 540-541

Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham: A Novel Solution for Chip-Level Functional Timing Verification. VTS 1997: 137-142

Magdy S. Abadir, Jacob A. Abraham, H. Hao, C. Hunter, Wayne M. Needham, Ron G. Walther: Microprocessor Test and Validation: Any New Avenues? VTS 1997: 458-464

Ashok Balivada, Jin Chen, Jacob A. Abraham: Analog Testing with Time Response Parameters. IEEE Design & Test of Computers 13(2): 18-25 (1996)

Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: A unified approach for fault simulation of linear mixed-signal circuits. J. Electronic Testing 9(1-2): 29-41 (1996)

V. S. S. Nair, Jacob A. Abraham, Prithviraj Banerjee: Efficient Techniques for the Analysis of Algorithm-Based Fault Tolerance (ABFT) Schemes. IEEE Trans. Computers 45(4): 499-503 (1996)

Daniel G. Saab, Youssef Saab, Jacob A. Abraham: Automatic test vector cultivation for sequential VLSI circuits using genetic algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 15(10): 1278-1285 (1996)

Prakash Arunachalam, Jacob A. Abraham, Manuel A. d'Abreu: A Hierarchal Approach for Power Reduction in VLSI Chips. Great Lakes Symposium on VLSI 1996: 182-

Sankaran Karthik, Mark Aitken, Glidden Martin, Srinivasu Pappula, Bob Stettler, Praveen Vishakantaiah, Manuel A. d'Abreu, Jacob A. Abraham: Distributed Mixed Level Logic and Fault Simulation on the Pentium® Pro Microprocessor. ITC 1996: 160-166

Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Hoskote: A Unified Framework for Design Validation and Manufacturing Test. ITC 1996: 875-884

Jacob A. Abraham, Gopi Ganapathy: Practical Test and DFT for Next Generation VLSI. VLSI Design 1996: 3

Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell: On More Efficient Combinational ATPG Using Functional Learning. VLSI Design 1996: 107-110

Abhijit Chatterjee, Rathish Jayabharathi, Pankaj Pant, Jacob A. Abraham: Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages. VTS 1996: 354-361

Hong Helena Zheng, Ashok Balivada, Jacob A. Abraham: A novel test generation approach for parametric faults in linear analog circuits . VTS 1996: 470-475

Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham: FERRARI: A Flexible Software-Based Fault and Error Injection System. IEEE Trans. Computers 44(2): 248-260 (1995)

Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell: Automated verification of temporal properties specified as state machines in VHDL. Great Lakes Symposium on VLSI 1995: 100-105

Yatin Vasant Hoskote, Dinos Moundanos, Jacob A. Abraham: Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. ICCD 1995: 532-537

Jawahar Jain, Dinos Moundanos, James R. Bitner, Jacob A. Abraham, Donald S. Fussell, Don E. Ross: Efficient variable ordering and partial representation algorithm. VLSI Design 1995: 81-86

Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham: Efficient multisine testing of analog circuits. VLSI Design 1995: 234-238

Ashok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham: Verification of transient response of linear analog circuits. VTS 1995: 42-47

Hoon Chang, Jacob A. Abraham: An efficient critical path tracing algorithm for sequential circuits. Microprocessing and Microprogramming 40(10-12): 913-916 (1994)

Marc E. Levitt, Kaushik Roy, Jacob A. Abraham: BiCMOS logic testing. IEEE Trans. VLSI Syst. 2(2): 241-248 (1994)

Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther: Microprocessor Testing: Which Technique is Best? (Panel). DAC 1994: 294

James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS 1994: 266-275

Daniel G. Saab, Youssef Saab, Jacob A. Abraham: Iterative [simulation-based genetics + deterministic techniques]= complete ATPG0. ICCAD 1994: 40-43

Abhijit Chatterjee, Jacob A. Abraham: RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults. ICCAD 1994: 340-343

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: A Signature Analyzer for Analog and Mixed-signal Circuits. ICCD 1994: 284-287

Edwin de Angel, Earl E. Swartzlander Jr., Jacob A. Abraham: A New Asynchronous Multiplier Using Enable/Disable CMOS Differential Logic. ICCD 1994: 302-305

S. Surya, Pradip Bose, Jacob A. Abraham: Architectural Performance Verification: PowerPC^TM Processors. ICCD 1994: 344-347

Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell: Verification of Circuits Described in VHDL through Extraction of Design Intent. VLSI Design 1994: 417-420

Thomas Thomas, Praveen Vishakantaiah, Jacob A. Abraham: Impact of behavioral modifications for testability. VTS 1994: 427-432

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: Fault simulation of linear analog circuits. J. Electronic Testing 4(4): 345-360 (1993)

Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham: VLSI logic and fault simulation on general-purpose parallel computers. IEEE Trans. on CAD of Integrated Circuits and Systems 12(3): 446-460 (1993)

Robert B. Mueller-Thuns, Daniel G. Saab, Robert F. Damiano, Jacob A. Abraham: Benchmarking Parallel Processing Platforms: An Applications Perspective. IEEE Trans. Parallel Distrib. Syst. 4(8): 947-954 (1993)

Hoon Chang, Jacob A. Abraham: VIPER: An Efficient Vigorously Sensitizable Path Extractor. DAC 1993: 112-117

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: DRAFTS: Discretized Analog Circuit Fault Simulator. DAC 1993: 509-514

Gopi Ganapathy, Jacob A. Abraham: Selective Pseudo Scan: Combinational ATPG with Reduced Scan in a Full Custom RISC Microprocessor. DAC 1993: 550-555

Praveen Vishakantaiah, Jacob A. Abraham: Impact of Behavioral Learning on the Compilation of Sequential Circuit Tests. FTCS 1993: 370-379

Naveena Nagi, Abhijit Chatterjee, Ashok Balivada, Jacob A. Abraham: Fault-based automatic test generator for linear analog circuits. ICCAD 1993: 88-91

Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir: AMBIANT: Automatic Generation of Behavioral Modifications for Testability. ICCD 1993: 63-66

Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham: MIXER: Mixed-Signal Fault Simulator. ICCD 1993: 568-571

Praveen Vishakantaiah, Jacob A. Abraham, Daniel G. Saab: CHEETA: Composition of Hierarchical Sequential Tests Using ATKET. ITC 1993: 606-615

Sankaran Karthik, Jacob A. Abraham, Raymond P. Voith: Optimizations for Behavioral/RTL Simulation. VLSI Design 1993: 311-316

Chun-Hung Chen, Jacob A. Abraham: Generation and evaluation of current and logic tests for switch-level sequential circuits. J. Electronic Testing 3(4): 359-366 (1992)

Jawahar Jain, Jacob A. Abraham, James R. Bitner, Donald S. Fussell: Probabilistic Verification of Boolean Functions. Formal Methods in System Design 1(1): 61-115 (1992)

V. S. S. Nair, Yatin Vasant Hoskote, Jacob A. Abraham: Probabilistic Evaluation of On-Line Checks in Fault-Tolerant Multiprocessor Systems. IEEE Trans. Computers 41(5): 532-541 (1992)

Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham: Test compaction for sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 260-267 (1992)

Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir: Automatic Test Knowledge Extraction from VHDL (ATKET). DAC 1992: 273-278

Junsheng Long, W. Kent Fuchs, Jacob A. Abraham: Compiler-Assisted Static Checkpoint Insertion. FTCS 1992: 58-65

Ghani A. Kanawati, Nasser A. Kanawati, Jacob A. Abraham: FERRARI: A Tool for The Validation of System Dependability Properties. FTCS 1992: 336-344

Daniel G. Saab, Youssef Saab, Jacob A. Abraham: CRIS: a test cultivation program for sequential VLSI circuits. ICCAD 1992: 216-219

Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu: Automatic test generation for linear digital systems with bi-level search using matrix transform methods. ICCAD 1992: 224-228

Sankaran Karthik, Jacob A. Abraham: Distributed VLSI Simulation on a Network of Workstations. ICCD 1992: 508-511

John Moondanos, Jacob A. Abraham: Sequential Redundancy Identification Using Verification Techniques. ITC 1992: 197-205

Abhijit Chatterjee, Jacob A. Abraham: Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling. J. Electronic Testing 2(4): 351-372 (1991)

Abhijit Chatterjee, Jacob A. Abraham: Test Generation for Iterative Logic Arrays Based on an N-Cube of Cell States Model. IEEE Trans. Computers 40(10): 1133-1148 (1991)

Jawahar Jain, Jim Bitner, Donald S. Fussell, Jacob A. Abraham: Probabilistic Design Verification. ICCAD 1991: 468-471

Sankaran Karthik, Indira de Souza, Joseph T. Rahmeh, Jacob A. Abraham: Interlock Schemes for Micropiplines: Application to a Self-Timed Rebound Sorter. ICCD 1991: 393-396

Chun-Hung Chen, Jacob A. Abraham: High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms. ITC 1991: 615-622

Gopi Ganapathy, Jacob A. Abraham: Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. ITC 1991: 848-857

Daniel G. Saab, Robert B. Mueller-Thuns, David Blaauw, Joseph T. Rahmeh, Jacob A. Abraham: Hierarchical multi-level fault simulation of large systems. J. Electronic Testing 1(2): 139-149 (1990)

V. S. S. Nair, Jacob A. Abraham: Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays. IEEE Trans. Computers 39(4): 426-435 (1990)

Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham: Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. IEEE Trans. Computers 39(9): 1132-1145 (1990)

Abhijit Chatterjee, Jacob A. Abraham: The Testability of Generalized Counters Under Multiple Faulty Cells. IEEE Trans. Computers 39(11): 1378-1385 (1990)

Ramachandra P. Kunda, Jacob A. Abraham, Bharat Deep Rathi, Prakash Narain: Speed Up of Test Generation Using High-Level Primitives. DAC 1990: 594-599

David T. Blaauw, Daniel G. Saab, Junsheng Long, Jacob A. Abraham: Derivation of signal flow for switch-level simulation. EURO-DAC 1990: 301-305

Kaushik Roy, Jacob A. Abraham: High level test generation using data flow descriptions. EURO-DAC 1990: 480-484

Suku Nair, Jacob A. Abraham: Hierarchical design and analysis of fault-tolerant multiprocessor systems using concurrent error detection. FTCS 1990: 130-137

David Blaauw, Robert B. Mueller-Thuns, Daniel G. Saab, Prithviraj Banerjee, Jacob A. Abraham: SNEL: A Switch-Level Simulator Using Multiple Levels of Functional Abstraction. ICCAD 1990: 66-69

Chun-Hung Chen, Jacob A. Abraham: Mixed-Level Sequential Test Generation Using a Nine-Valued Relaxation Algorithm. ICCAD 1990: 230-233

Junsheng Long, W. Kent Fuchs, Jacob A. Abraham: Forward Recovery Using Checkpointing in Parallel Systems. ICPP (1) 1990: 272-275

John C. Chan, Jacob A. Abraham: A study of faulty signatures using a matrix formulation. ITC 1990: 553-561

Robert B. Mueller-Thuns, Daniel G. Saab, Jacob A. Abraham: Design of a scalable parallel switch-level simulator for VLSI. SC 1990: 615-624

David Blaauw, Daniel G. Saab, Robert B. Mueller-Thuns, Jacob A. Abraham, Joseph T. Rahmeh: Automatic Generation of Behavioral Models from Switch-Level Descriptions. DAC 1989: 179-184

Carol V. Gura, Jacob A. Abraham: Average Interconnection Length and Interconnection Distribution Based on Rent's Rule. DAC 1989: 574-577

Kaushik Roy, Jacob A. Abraham: A Novel Approach to Accurate Timing Verification Using RTL Descriptions. DAC 1989: 638-641

Jacob A. Abraham: Advances in VLSI-Testing. IFIP Congress 1989: 1013-1018

Kurt H. Thearling, Jacob A. Abraham: An Easily Computed Functional Level Testability Measure. ITC 1989: 381-390

Marc E. Levitt, Jacob A. Abraham: The Economics of Scan Design. ITC 1989: 869-874

Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant FFT Networks. IEEE Trans. Computers 37(5): 548-561 (1988)

Carol V. Gura, Jacob A. Abraham: Improved Methods of Simulating RLC Couple and Uncoupled Transmission Lines Based on the Method of Characteristics. DAC 1988: 300-305

Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers: Fault Simulation in a Distributed Environment. DAC 1988: 686-691

Suku Nair, Jacob A. Abraham: General linear codes for fault-tolerant matrix operations on processor arrays. FTCS 1988: 180-185

Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Jacob A. Abraham: An evaluation of system-level fault tolerance on the Intel hypercube multiprocessor. FTCS 1988: 362-367

Jing-Yang Jou, Jacob A. Abraham: Fault-Tolerant Algorithms and Architectures for Real Time Signal Processing. ICPP (1) 1988: 359-362

M. J. Marlett, Jacob A. Abraham: DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests. ITC 1988: 839-844

Abhijit Chatterjee, Jacob A. Abraham: On the C-Testability of Generalized Counters. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 713-726 (1987)

William A. Rogers, John F. Guzolek, Jacob A. Abraham: Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations. IEEE Trans. on CAD of Integrated Circuits and Systems 6(5): 848-862 (1987)

W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham: Comparison and Diagnosis of Large Replicated Files. IEEE Trans. Software Eng. 13(1): 15-22 (1987)

Prithviraj Banerjee, Jacob A. Abraham: Bounds on Algorithm-Based Fault Tolerance in Multiple Processor Systems. IEEE Trans. Computers 35(4): 296-306 (1986)

Timothy C. K. Chou, Jacob A. Abraham: Distributed Control of Computer Systems. IEEE Trans. Computers 35(6): 564-567 (1986)

Hsi-Ching Shih, Joseph T. Rahmeh, Jacob A. Abraham: FAUST: An MOS Fault Simulator with Timing Information. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 557-563 (1986)

Hsi-Ching Shih, Jacob A. Abraham: Transistor-level test generation for physical failures in CMOS circuits. DAC 1986: 243-249

Chien-Yi Chen, Jacob A. Abraham: On the Design of Fault-Tolerant Systolic Arrays with Linear Cells. FJCC 1986: 400-409

Kien A. Hua, Jacob A. Abraham: Design of Systems with Concurrent Error Detection Using Software Redundancy. FJCC 1986: 826-835

Jacob A. Abraham: Research in Reliable VLSI Architectures at the University of Illinois. FJCC 1986: 890-893

Hongtao P. Chang, William A. Rogers, Jacob A. Abraham: Structured Functional Level Test Generation Using Binary Decision Diagrams. ITC 1986: 97-104

Robert H. Fujii, Jacob A. Abraham: Approaches to Circuit Level Design for Testability. ITC 1986: 480-483

Prithviraj Banerjee, Jacob A. Abraham: A Probabilistic Model of Algorithm-Based Fault Tolerance in Array Processors for Real-Time Systems. RTSS 1986: 72-78

W. Kent Fuchs, Kun-Lung Wu, Jacob A. Abraham: Low-Cost Comparison and Diagnosis of Large Remotely Located Files. Symposium on Reliability in Distributed Software and Database Systems 1986: 67-73

Niraj K. Jha, Jacob A. Abraham: Design of Testable CMOS Logic Circuits Under Arbitrary Delays. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 264-269 (1985)

Prithviraj Banerjee, Jacob A. Abraham: A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 312-321 (1985)

William A. Rogers, Jacob A. Abraham: High level hierarchical fault simulation techniques. ACM Conference on Computer Science 1985: 89-97

Peter Y.-T. Hsu, Joseph T. Rahmeh, Edward S. Davidson, Jacob A. Abraham: TIDBITS: Speedup Via Time-Delay Bit-Slicing in ALU Design for VLSI Technology. ISCA 1985: 28-35

Robert H. Fujii, Jacob A. Abraham: Self-Test for Microprocessors. ITC 1985: 356-361

William A. Rogers, Jacob A. Abraham: CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator. ITC 1985: 710-716

Dhananjay Brahme, Jacob A. Abraham: Functional Testing of Microprocessors. IEEE Trans. Computers 33(6): 475-485 (1984)

Kuang-Hua Huang, Jacob A. Abraham: Algorithm-Based Fault Tolerance for Matrix Operations. IEEE Trans. Computers 33(6): 518-528 (1984)

Prithviraj Banerjee, Jacob A. Abraham: Fault-Secure Algorithms for Multiple-Processor Systems. ISCA 1984: 279-287

Ramaswami Dandapani, Janak H. Patel, Jacob A. Abraham: Design of Test Pattern Generators for Built-In Test. ITC 1984: 315-319

Timothy C. K. Chou, Jacob A. Abraham: Load Redistribution Under Failure in Distributed Systems. IEEE Trans. Computers 32(9): 799-808 (1983)

Richard L. Norton, Jacob A. Abraham: Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets. ISCA 1983: 277-282

W. Kent Fuchs, Jacob A. Abraham, Kuang-Hua Huang: Concurrent Error Detection in VLSI Interconnection Networks. ISCA 1983: 309-315

Jacob A. Abraham: Incorporating Test Technology into an Undergraduate Curriculum. ITC 1983: 162

Prithviraj Banerjee, Jacob A. Abraham: Generating Tests for Physical Failures in MOS Logic Circuits. ITC 1983: 554-559

Timothy C. K. Chou, Jacob A. Abraham: Load Balancing in Distributed Systems. IEEE Trans. Software Eng. 8(4): 401-412 (1982)

Pradip Bose, Jacob A. Abraham: Test generation for programmable logic arrays. DAC 1982: 574-580

Kuang-Hua Huang, Jacob A. Abraham: Efficient parallel algorithms for processor arrays. ICPP 1982: 268-279

Richard L. Norton, Jacob A. Abraham: Using write back cache to improve performance of multi-user multiprocessors. ICPP 1982: 326-331

Jacob A. Abraham, Daniel Gajski: Design of Testable Structures Defined by Simple Loops. IEEE Trans. Computers 30(11): 875-884 (1981)

Jacob A. Abraham: Functional Level Test Generation for Complex Digital Systems. ITC 1981: 461-462

Satish M. Thatte, Jacob A. Abraham: Test Generation for Microprocessors. IEEE Trans. Computers 29(6): 429-441 (1980)

Ravindra Nair, Satish M. Thatte, Jacob A. Abraham: Efficient Algorithms for Testing Semiconductor Random-Access Memories. IEEE Trans. Computers 27(6): 572-576 (1978)