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 | 2013 | |
|---|---|---|
| j20 |      | Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio: On the design of energy-efficient hardware transactional memory systems. Concurrency and Computation: Practice and Experience 25(6): 862-880 (2013) |
| j19 | | J. Rubén Titos Gil, Manuel E. Acacio, José M. García: Efficient Eager Management of Conflicts for Scalable Hardware Transactional Memory. IEEE Trans. Parallel Distrib. Syst. 24(1): 59-71 (2013) |
| c54 | | Epifanio Gaona-Ramírez, José L. Abellán, Manuel E. Acacio, Juan Fernández: Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory. ARCS 2013: 220-231 |
| 2012 | ||
| j18 | | J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Tim Harris, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero: Hardware transactional memory with software-defined conflicts. TACO 8(4): 31 (2012) |
| j17 | | Alberto Ros, Blas Cuesta Saez, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato: Extending Magny-Cours Cache Coherence. IEEE Trans. Computers 61(5): 593-606 (2012) |
| j16 | | José M. Cecilia, José L. Abellán, Juan Fernández, Manuel E. Acacio, José M. García, Manuel Ujaldon: Stencil computations on heterogeneous platforms for the Jacobi method: GPUs versus Cell BE. The Journal of Supercomputing 62(2): 787-803 (2012) |
| j15 | | José L. Abellán, Juan Fernández, Manuel E. Acacio: Efficient Hardware Barrier Synchronization in Many-Core CMPs. IEEE Trans. Parallel Distrib. Syst. 23(8): 1453-1466 (2012) |
| c53 | | José L. Abellán, Juan Fernández Peinador, Manuel E. Acacio, Davide Bertozzi, Daniele Bortolotti, Andrea Marongiu, Luca Benini: Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs. DATE 2012: 491-496 |
| c52 | | Mario Lodde, Jose Flich, Manuel E. Acacio: Dynamic Last-Level Cache Allocation to Reduce Area and Power Overhead in Directory Coherence Protocols. Euro-Par 2012: 206-218 |
| c51 | | Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström: π-TM: Pessimistic invalidation for scalable lazy hardware transactional memory. HPCA 2012: 141-152 |
| c50 | | Manuel E. Acacio, Javier Cuenca, Lorenzo Fernández, Ricardo Fernández Pascual, Joaquín Cervera, Domingo Giménez, M. Carmen Garrido, Juan A. Sánchez-Laguna, José Guillén, Juan Alejandro Palomino Benito, María-Eugenia Requena: An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain. IPDPS Workshops 2012: 1289-1294 |
| c49 | | Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García: ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED 2012: 51-56 |
| c48 | | Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Manuel E. Acacio, Juan Fernández: Dynamic Serialization: Improving Energy Consumption in Eager-Eager Hardware Transactional Memory Systems. PDP 2012: 221-228 |
| c47 | | Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio: Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD 2012: 43-50 |
| 2011 | ||
| c46 | | Anurag Negi, Per Stenström, J. Rubén Titos Gil, Manuel E. Acacio, José M. García: Pi-TM: Pessimistic Invalidation for Scalable Lazy Hardware Transactional Memory. PACT 2011: 203-204 |
| c45 | | Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström: Eager Meets Lazy: The Impact of Write-Buffering on Hardware Transactional Memory. ICPP 2011: 73-82 |
| c44 | | J. Rubén Titos Gil, Anurag Negi, Manuel E. Acacio, José M. García, Per Stenström: ZEBRA: a data-centric, hybrid-policy hardware transactional memory design. ICS 2011: 53-62 |
| c43 | | Anurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström: The Impact of Non-coherent Buffers on Lazy Hardware Transactional Memory Systems. IPDPS Workshops 2011: 700-707 |
| c42 | | José L. Abellán, Juan Fernández, Manuel E. Acacio: GLocks: Efficient Support for Highly-Contended Locks in Many-Core CMPs. IPDPS 2011: 893-905 |
| 2010 | ||
| j14 | | Alberto Ros, Manuel E. Acacio, José M. García: A scalable organization for distributed directories. Journal of Systems Architecture - Embedded Systems Design 56(2-3): 77-87 (2010) |
| j13 | | Antonio Flores, Manuel E. Acacio, Juan L. Aragón: Exploiting address compression and heterogeneous interconnects for efficient message management in tiled CMPs. Journal of Systems Architecture - Embedded Systems Design 56(9): 429-441 (2010) |
| j12 | | Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Heterogeneous Interconnects for Energy-Efficient Message Management in CMPs. IEEE Trans. Computers 59(1): 16-28 (2010) |
| j11 | | José L. Abellán, Juan Fernández, Manuel E. Acacio: Characterizing the basic synchronization and communication operations in Dual Cell-based Blades through CellStats. The Journal of Supercomputing 53(2): 247-268 (2010) |
| j10 | | Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level. IEEE Trans. Parallel Distrib. Syst. 21(8): 1117-1131 (2010) |
| j9 | | Alberto Ros, Manuel E. Acacio, José M. García: A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 21(12): 1779-1792 (2010) |
| c41 | | José L. Abellán, Juan Fernández, Manuel E. Acacio: Efficient and scalable barrier synchronization for many-core CMPs. Conf. Computing Frontiers 2010: 73-74 |
| c40 | | Alberto Ros, Manuel E. Acacio: Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. Euro-Par Workshops 2010: 87-97 |
| c39 | | Alberto Ros, Blas Cuesta, Ricardo Fernández Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato: EMC2: Extending Magny-Cours coherence for large-scale servers. HiPC 2010: 1-10 |
| c38 | | José L. Abellán, Juan Fernández, Manuel E. Acacio: A G-Line-Based Network for Fast and Efficient Barrier Synchronization in Many-Core CMPs. ICPP 2010: 267-276 |
| c37 | | Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Energy-Efficient Hardware Prefetching for CMPs Using Heterogeneous Interconnects. PDP 2010: 147-154 |
| c36 | | Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio: Characterizing Energy Consumption in Hardware Transactional Memory Systems. SBAC-PAD 2010: 9-16 |
| 2009 | ||
| c35 | | Alberto Ros, Manuel E. Acacio, José M. García: Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT 2009: 11-27 |
| c34 | | Epifanio Gaona-Ramírez, Juan Fernández, Manuel E. Acacio: Fast and Efficient Synchronization and Communication Collective Primitives for Dual Cell-Based Blades. Euro-Par 2009: 900-911 |
| c33 | | Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García: Distance-aware round-robin mapping for large NUCA caches. HiPC 2009: 79-88 |
| c32 | | J. Rubén Titos Gil, Manuel E. Acacio, José M. García Carrasco: Speculation-based conflict resolution in hardware transactional memory. IPDPS 2009: 1-12 |
| c31 | | Joaquín Franco, Gregorio Bernabé, Juan Fernández, Manuel E. Acacio: A Parallel Implementation of the 2D Wavelet Transform Using CUDA. PDP 2009: 111-118 |
| 2008 | ||
| j8 | | Alberto Ros, Ricardo Fernández Pascual, Manuel E. Acacio, José M. García: Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distrib. Comput. 68(11): 1413-1424 (2008) |
| j7 | | Antonio Flores, Juan L. Aragón, Manuel E. Acacio: An energy consumption characterization of on-chip interconnection networks for tiled CMP architectures. The Journal of Supercomputing 45(3): 341-364 (2008) |
| j6 | | Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures. IEEE Trans. Parallel Distrib. Syst. 19(8): 1044-1056 (2008) |
| c30 |  | Alberto Ros, Manuel E. Acacio, José M. García: Scalable Directory Organization for Tiled CMP Architectures. CDES 2008: 112-118 |
| c29 | | Juan Fernández, Manuel E. Acacio, Gregorio Bernabé, José L. Abellán, Joaquín Franco: Multicore Platforms for Scientific Computing: Cell BE and NVIDIA Tesla. CSC 2008: 167-173 |
| c28 | | Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: A fault-tolerant directory-based cache coherence protocol for CMP architectures. DSN 2008: 267-276 |
| c27 | | J. Rubén Titos Gil, Manuel E. Acacio, José M. García: Directory-Based Conflict Detection in Hardware Transactional Memory. HiPC 2008: 541-554 |
| c26 | | Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: Fault-Tolerant Cache Coherence Protocols for CMPs: Evaluation and Trade-Offs. HiPC 2008: 555-568 |
| c25 | | José L. Abellán, Juan Fernández, Manuel E. Acacio: Characterizing the Basic Synchronization and Communication Operations in Dual Cell-Based Blades. ICCS (1) 2008: 456-465 |
| c24 | | Antonio Flores, Manuel E. Acacio, Juan L. Aragón: Address Compression and Heterogeneous Interconnects for Energy-Efficient High-Performance in Tiled CMPs. ICPP 2008: 295-303 |
| c23 | | Alberto Ros, Manuel E. Acacio, José M. García: DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS 2008: 1-11 |
| c22 | | J. Rubén Titos Gil, Manuel E. Acacio, José M. García Carrasco: Characterization of Conflicts in Log-Based Transactional Memory (LogTM). PDP 2008: 30-37 |
| c21 | | José L. Abellán, Juan Fernández, Manuel E. Acacio: CellStats: A Tool to Evaluate the Basic Synchronization and Communication Operations of the Cell BE. PDP 2008: 261-268 |
| 2007 | ||
| j5 | | Gregorio Bernabé, Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José González: An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology. Parallel Computing 33(1): 54-72 (2007) |
| c20 | | Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Sim-PowerCMP: A Detailed Simulator for Energy Consumption Analysis in Future Embedded CMP Architectures. AINA Workshops (1) 2007: 752-757 |
| c19 | | Antonio Flores, Juan L. Aragón, Manuel E. Acacio: Efficient Message Management in Tiled CMP Architectures Using a Heterogeneous Interconnection Network. HiPC 2007: 133-146 |
| c18 | | Alberto Ros, Manuel E. Acacio, José M. García: Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC 2007: 147-160 |
| c17 | | Ricardo Fernández Pascual, José M. García, Manuel E. Acacio, José Duato: A Low Overhead Fault Tolerant Coherence Protocol for CMP Architectures. HPCA 2007: 157-168 |
| 2006 | ||
| c16 | | Alberto Ros, Manuel E. Acacio, José M. García: An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers 2006: 321-330 |
| c15 | | Francisco J. Villa, Manuel E. Acacio, José M. García: On the Evaluation of Dense Chip-Multiprocessor Architectures. ICSAMOS 2006: 21-27 |
| 2005 | ||
| j4 | | Francisco J. Villa, Manuel E. Acacio, José M. García: Evaluating IA-32 web servers through simics: a practical experience. Journal of Systems Architecture 51(4): 251-264 (2005) |
| j3 | | Manuel E. Acacio, José González, José M. García, José Duato: A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors. IEEE Trans. Parallel Distrib. Syst. 16(1): 67-79 (2005) |
| c14 | | Alberto Ros, Manuel E. Acacio, José M. García: A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. Euro-Par 2005: 582-591 |
| c13 | | Francisco J. Villa, Manuel E. Acacio, José M. García: Memory Subsystem Characterization in a 16-Core Snoop-Based Chip-Multiprocessor Architecture. HPCC 2005: 213-222 |
| c12 | | Ricardo Fernández Pascual, José M. García, Gregorio Bernabé, Manuel E. Acacio: Optimizing a 3D-FWT Video Encoder for SMPs and HyperThreading Architectures. PDP 2005: 76-83 |
| 2004 | ||
| j2 | | Manuel E. Acacio, José González, José M. García, José Duato: An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration. IEEE Trans. Parallel Distrib. Syst. 15(8): 755-768 (2004) |
| c11 | | Francisco J. Villa, Manuel E. Acacio, José M. García: On the Evaluation of x86 Web Servers Using Simics: Limitations and Trade-Offs. International Conference on Computational Science 2004: 541-544 |
| 2002 | ||
| j1 | | Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel: MPI-Delphi: an MPI implementation for visual programming environments and heterogeneous computing. Future Generation Comp. Syst. 18(3): 317-333 (2002) |
| c10 | | Manuel E. Acacio, José González, José M. García, José Duato: The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors. IEEE PACT 2002: 155-164 |
| c9 | | Manuel E. Acacio, José González, José M. García, José Duato: A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors. IPDPS 2002 |
| c8 | | Manuel E. Acacio, José González, José M. García, José Duato: Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration. PDP 2002: 368-375 |
| c7 | | Manuel E. Acacio, José González, José M. García, José Duato: Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture. SC 2002: 1-12 |
| 2001 | ||
| c6 | | Manuel E. Acacio, José González, José M. García, José Duato: A New Scalable Directory Architecture for Large-Scale Multiprocessors. HPCA 2001: 97-106 |
| 1999 | ||
| c5 | | Manuel E. Acacio, Óscar Cánovas Reverte, José M. García, Pedro E. López-de-Teruel: An Evaluation of Parallel Computing in PC Clusters with Fast Ethernet. ACPC 1999: 570-571 |
| c4 | | Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio, Óscar Cánovas Reverte: P-EDR: An Algorithm for Parallel Implementation of Parzen Density Estimation from Uncertain Observations. IPPS/SPDP 1999: 563-568 |
| c3 | | Pedro E. López-de-Teruel, José M. García, Manuel E. Acacio: The Parallel EM Algorithm and its Applications in Computer Vision. PDPTA 1999: 571-578 |
| c2 | | Manuel E. Acacio, José M. García, Pedro E. López-de-Teruel: A Performance Evaluation of P-EDR in Different Parallel Environments. PDPTA 1999: 744-750 |
| c1 | | Manuel E. Acacio, Pedro E. López-de-Teruel, José M. García, Óscar Cánovas Reverte: The MPI-Delphi Interface: A Visual Programming Environment for Clusters of Workstations. PDPTA 1999: 1730-1736 |
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