Astrit Ademaj

Marco Serafini, Péter Bokor, Neeraj Suri, Jonny Vinter, Astrit Ademaj, Wolfgang Brandstätter, Fulvio Tagliabo, Jens Koch: Application-Level Diagnostic and Membership Protocols for Generic Time-Triggered Systems. IEEE Trans. Dependable Sec. Comput. 8(2): 177-193 (2011)

Vaclav Mikolasek, Astrit Ademaj, Stanislav Racek: Segmentation of standard ethernet messages in the time-triggered ethernet. ETFA 2008: 392-399

Marco Serafini, Neeraj Suri, Jonny Vinter, Astrit Ademaj, Wolfgang Brandstätter, Fulvio Tagliabo, Jens Koch: A Tunable Add-On Diagnostic Protocol for Time-Triggered Systems. DSN 2007: 164-174

Klaus Steinhammer, Astrit Ademaj: Hardware Implementation of the Time-Triggered Ethernet Controller. IESS 2007: 325-338

Jonny Vinter, Henrik Eriksson, Astrit Ademaj, Bernhard Leiner, Martin Schlager: Experimental Evaluation of the DECOS Fault-Tolerant Communication Layer. SAFECOMP 2007: 264-269

Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik: Combination of clock-state and clock-rate correction in fault-tolerant distributed systems. Real-Time Systems 33(1-3): 139-173 (2006)

Astrit Ademaj, Hermann Kopetz, Petr Grillinger, Klaus Steinhammer, Alexander Hanzlik: Fault-Tolerant Time-Triggered Ethernet Configuration with Star Topology. ARCS Workshops 2006: 95-105

Klaus Steinhammer, Petr Grillinger, Astrit Ademaj, Hermann Kopetz: A time-triggered ethernet (TTE) switch. DATE 2006: 794-799

Philipp Peti, Roman Obermaisser, Astrit Ademaj, Hermann Kopetz: A Maintenance-Oriented Fault Model for the DECOS Integrated Diagnostic Architecture. IPDPS 2005

Hermann Kopetz, Astrit Ademaj, Petr Grillinger, Klaus Steinhammer: The Time-Triggered Ethernet (TTE) Design. ISORC 2005: 22-33

Hermann Kopetz, Astrit Ademaj, Alexander Hanzlik: Integration of Internal and External Clock Synchronization by the Combination of Clock-State and Clock-Rate Correction in Fault-Tolerant Distributed Systems. RTSS 2004: 415-425

Astrit Ademaj, Håkan Sivencrona, Günther Bauer, Jan Torin: Evaluation of Fault Handling of the Time-Triggered Architecture with Bus and Star Topology. DSN 2003: 123-132

Astrit Ademaj: A Methodology for Dependability Evaluation of the Time-Triggered Architecture Using Software Implemented Fault Injection. EDCC 2002: 172-190

Astrit Ademaj: Slightly-off-specification failures in the time-triggered architecture. HLDVT 2002: 7-12

Idriz Smaili, Astrit Ademaj: Setting break-points in distributed time-triggered architecture. HLDVT 2002: 57-62

Astrit Ademaj, Petr Grillinger, Pavel Herout, Jan Hlavicka: Fault Tolerance Evaluation Using Two Software Based Fault Injection Methods. IOLTW 2002: 21-25