| 2013 | ||
|---|---|---|
| j17 | Steven Hsu, Amit Agarwal, Mark Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram K. Krishnamurthy: A 280 mV-to-1.1 V 256b Reconfigurable SIMD Vector Permutation Engine With 2-Dimensional Shuffle in 22 nm Tri-Gate CMOS. J. Solid-State Circuits 48(1): 118-127 (2013) | |
| j16 | Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar: A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. J. Solid-State Circuits 48(1): 128-139 (2013) | |
| j15 | Amit Agarwal, Jason Cong, Brian Tagiku: The survivability of design-specific spare placement in FPGA architectures with high defect rates. ACM Trans. Design Autom. Electr. Syst. 18(2): 33 (2013) | |
| 2012 | ||
| j14 | Sanu Mathew, Suresh Srinivasan, Mark Anders, Himanshu Kaul, Steven Hsu, Farhana Sheikh, Amit Agarwal, Sudhir Satpathy, Ram Krishnamurthy: 2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. J. Solid-State Circuits 47(11): 2807-2821 (2012) | |
| c41 | Himanshu Kaul, Mark Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar: Near-threshold voltage (NTV) design: opportunities and challenges. DAC 2012: 1153-1158 | |
| c40 | Amit Agarwal, Steven Hsu, Sanu Mathew, Mark Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy: A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. ESSCIRC 2012: 177-180 | |
| c39 | Steven Hsu, Amit Agarwal, Mark Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy: A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. ISSCC 2012: 178-180 | |
| c38 | Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar: A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC 2012: 182-184 | |
| c37 | Farhana Sheikh, Sanu Mathew, Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar: A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC 2012: 184-186 | |
| 2011 | ||
| j13 | Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, Shay Gueron, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark Anders, Ram Krishnamurthy: 53 Gbps Native GF(2 4) 2 Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors. J. Solid-State Circuits 46(4): 767-776 (2011) | |
| c36 | Amit Agarwal, Steven Hsu, Sanu Mathew, Mark Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy: A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. ESSCIRC 2011: 83-86 | |
| c35 | Rangharajan Venkatesan, Amit Agarwal, Kaushik Roy, Anand Raghunathan: MACACO: Modeling and analysis of circuits for approximate computing. ICCAD 2011: 667-673 | |
| 2010 | ||
| j12 | Nandita Dukkipati, Tiziana Refice, Yuchung Cheng, Jerry Chu, Tom Herbert, Amit Agarwal, Arvind Jain, Natalia Sutin: An argument for increasing TCP's initial congestion window. Computer Communication Review 40(3): 26-33 (2010) | |
| j11 | Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar: A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. J. Solid-State Circuits 45(1): 95-102 (2010) | |
| c34 | ||
| c33 | Mark Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar: A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC 2010: 110-111 | |
| c32 | Amit Agarwal, Sanu Mathew, Steven Hsu, Mark Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar: A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC 2010: 328-329 | |
| c31 | Hema Swetha Koppula, Krishna P. Leela, Amit Agarwal, Krishna Prasad Chitrapura, Sachin Garg, Amit Sasturkar: Learning URL patterns for webpage de-duplication. WSDM 2010: 381-390 | |
| 2009 | ||
| c30 | Amit Agarwal, Hema Swetha Koppula, Krishna P. Leela, Krishna Prasad Chitrapura, Sachin Garg, Pavan Kumar GM, Chittaranjan Haty, Anirban Roy, Amit Sasturkar: URL normalization for de-duplication of web pages. CIKM 2009: 1987-1990 | |
| c29 | Himanshu Kaul, Mark Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar: A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC 2009: 260-261 | |
| 2008 | ||
| j10 | Kwee Kim Lim, Yew-Soon Ong, Meng-Hiot Lim, Xianshun Chen, Amit Agarwal: Hybrid ant colony algorithms for path planning in sparse graphs. Soft Comput. 12(10): 981-994 (2008) | |
| j9 | Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy: Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput. IEEE Trans. Computers 57(7): 940-951 (2008) | |
| c28 | Amit Agarwal, Jayanthi Sivaswamy, Alka Rani, Taraprasad Das: Automatic Segmentation of Capillary Non-Perfusion in Retinal Angiograms. BIOSIGNALS (1) 2008: 170-177 | |
| c27 | Jayanthi Sivaswamy, Amit Agarwal, Mayank Chawla, Alka Rani, Taraprasad Das: Extraction of Capillary Non-perfusion from Fundus Fluorescein Angiogram. BIOSTEC (Selected Papers) 2008: 176-188 | |
| c26 | Vinayaka Pandit, Natwar Modani, Sougata Mukherjea, Amit Anil Nanavati, Sambuddha Roy, Amit Agarwal: Extracting dense communities from telecom call graphs. COMSWARE 2008: 82-89 | |
| c25 | Amit Agarwal, Jason Cong, Brian Tagiku: Fault tolerant placement and defect reconfiguration for nano-FPGAs. ICCAD 2008: 714-721 | |
| 2007 | ||
| j8 | Amit Agarwal, Meng-Hiot Lim, Meng Joo Er, Nguyen Trung Nghia: Rectilinear workspace partitioning for parallel coverage using multiple unmanned aerial vehicles. Advanced Robotics 21(1): 105-120 (2007) | |
| j7 | Elad Hazan, Amit Agarwal, Satyen Kale: Logarithmic regret algorithms for online convex optimization. Machine Learning 69(2-3): 169-192 (2007) | |
| j6 | Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies. IEEE Trans. VLSI Syst. 15(6): 660-671 (2007) | |
| c24 | Amit Agarwal, Noga Alon, Moses Charikar: Improved approximation for directed cut problems. STOC 2007: 671-680 | |
| 2006 | ||
| j5 | Bipul Chandra Paul, Amit Agarwal, Kaushik Roy: Low-power design techniques for scaled technologies. Integration 39(2): 64-89 (2006) | |
| j4 | Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim: Leakage Power Analysis and Reduction for Nanoscale Circuits. IEEE Micro 26(2): 68-80 (2006) | |
| c23 | Elad Hazan, Adam Kalai, Satyen Kale, Amit Agarwal: Logarithmic Regret Algorithms for Online Convex Optimization. COLT 2006: 499-513 | |
| c22 | Amit Agarwal, Elad Hazan, Satyen Kale, Robert E. Schapire: Algorithms for portfolio management based on the Newton method. ICML 2006: 9-16 | |
| c21 | Amit Agarwal, Ram Krishnamurthy: High-performance energy-efficient memory circuit technologies for sub-45nm technologies. SoCC 2006: 322 | |
| i1 | Amit Agarwal, Elad Hazan: Efficient Algorithms for Online Game Playing and Universal Portfolio Management. Electronic Colloquium on Computational Complexity (ECCC) 13(033) (2006) | |
| 2005 | ||
| j3 | Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy: A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. VLSI Syst. 13(1): 27-38 (2005) | |
| c20 | Amit Agarwal, Kunhyuk Kang, Kaushik Roy: Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations. ICCAD 2005: 736-741 | |
| c19 | Patrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy: A Soft Error Monitor Using Switching Current Detection. ICCD 2005: 185-192 | |
| c18 | Amit Agarwal, Meng-Hiot Lim, Meng Joo Er: Proportional Partition of Holed Rectilinear Region amongst Multiple URAVs. ICRA 2005: 1779-1784 | |
| c17 | Amit Agarwal, Meng-Hiot Lim, Meng Joo Er, Chan Yee Chew: ACO for a new TSP in region coverage. IROS 2005: 1717-1722 | |
| c16 | Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy: Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations. ISLPED 2005: 14-19 | |
| c15 | Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar: An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED 2005: 103-106 | |
| c14 | Elena Nabieva, Kam Jim, Amit Agarwal, Bernard Chazelle, Mona Singh: Whole-proteome prediction of protein function via graph-theoretic analysis of interaction maps. ISMB (Supplement of Bioinformatics) 2005: 302-310 | |
| c13 | Amit Agarwal, Moses Charikar, Konstantin Makarychev, Yury Makarychev: O(sqrt(log n)) approximation algorithms for min UnCut, min 2CNF deletion, and directed cut problems. STOC 2005: 573-581 | |
| 2004 | ||
| j2 | Frank Harary, Meng-Hiot Lim, Amit Agarwal, Donald C. Wunsch: Algorithms for derivation of structurally stable Hamiltonian signed graphs. Int. J. Comput. Math. 81(11): 1349-1356 (2004) | |
| c12 | Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy: Leakage in nano-scale technologies: mechanisms, impact and design considerations. DAC 2004: 6-11 | |
| c11 | Amit Agarwal, Meng-Hiot Lim, Chan Yee Chew, Tong Kiang Poo, Meng Joo Er, Yew Kong Leong: Solution to the Fixed Airbase Problem for Autonomous URAV Site Visitation Sequencing. GECCO (2) 2004: 850-858 | |
| c10 | Amit Agarwal, Meng-Hiot Lim, Maung Ye Win Kyaw, Meng Joo Er: Inflight Rerouting for an Unmanned Aerial Vehicle. GECCO (2) 2004: 859-868 | |
| c9 | Amit Agarwal, Bipul Chandra Paul, Kaushik Roy: A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies. IOLTS 2004: 149-154 | |
| c8 | Amit Agarwal, Meng-Hiot Lim, Lip Chien Woon: A divide and conquer algorithm for rectilinear region coverage. RAM 2004: 996-1001 | |
| c7 | Amit Agarwal, Kaushik Roy, Ram K. Krishnamurthy: A leakage-tolerant low-leakage register file with conditional sleep transistor. SoCC 2004: 241-244 | |
| 2003 | ||
| j1 | Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy: Gate leakage reduction for scaled devices using transistor stacking. IEEE Trans. VLSI Syst. 11(4): 716-730 (2003) | |
| c6 | Jim Blythe, Ewa Deelman, Yolanda Gil, Carl Kesselman, Amit Agarwal, Gaurang Mehta, Karan Vahi: The Role of Planning in Grid Computing. ICAPS 2003: 153-163 | |
| c5 | Amit Agarwal, Kaushik Roy, T. N. Vijaykumar: Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology. DATE 2003: 10778-10783 | |
| c4 | Amit Agarwal, Tarun Agarwal, Sumit Chopra, Anja Feldmann, Nils Kammenhuber, Piotr Krysta, Berthold Vöcking: An Experimental Study of k-Splittable Scheduling for DNS-Based Traffic Allocation. Euro-Par 2003: 230-235 | |
| c3 | Amit Agarwal, Kaushik Roy: A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. ISLPED 2003: 18-21 | |
| 2002 | ||
| c2 | Amit Agarwal, Hai Li, Kaushik Roy: DRG-cache: a data retention gated-ground cache for low power. DAC 2002: 473-478 | |
| 2001 | ||
| c1 | Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy: Reducing set-associative cache energy via way-prediction and selective direct-mapping. MICRO 2001: 54-65 | |
Colors in the list of coauthors
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