Vishwani D. Agrawal

Vishwani D. Agrawal: Editorial. J. Electronic Testing 29(1): 1-2 (2013)

Ozgur Sinanoglu, Vishwani D. Agrawal: Eliminating the Timing Penalty of Scan. J. Electronic Testing 29(1): 103-114 (2013)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 29(2): 121 (2013)

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal: Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. VLSI Design 2013: 267-272

Praveen Venkataramani, Vishwani D. Agrawal: Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. VLSI Design 2013: 273-278

Vishwani D. Agrawal: Editorial. J. Electronic Testing 28(1): 1 (2012)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 28(2): 151-152 (2012)

Mohammed Ashfaq Shukoor, Vishwani D. Agrawal: Diagnostic Test Set Minimization and Full-Response Fault Dictionary. J. Electronic Testing 28(2): 177-187 (2012)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 28(3): 263-264 (2012)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 28(4): 389-390 (2012)

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Defect Level and Fault Coverage in Coefficient Based Analog Circuit Testing. J. Electronic Testing 28(4): 541-549 (2012)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 28(5): 551-552 (2012)

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform Coefficients. J. Electronic Testing 28(5): 757-771 (2012)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 28(6): 773-774 (2012)

Kanad Chakraborty, Vishwani D. Agrawal: Data-Driven DPPM Estimation and Adaptive Fault Coverage Calibration Using MATLAB®. J. Electronic Testing 28(6): 869-875 (2012)

Suraj Sindia, Vishwani D. Agrawal: Tailoring Tests for Functional Binning of Integrated Circuits. ATS 2012: 95-100

Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh: Impact of process variations on computers used for image processing. ISCAS 2012: 1444-1447

Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal: Optimal power-constrained SoC test schedules with customizable clock rates. SoCC 2012: 271-276

Farhana Rashid, Vishwani D. Agrawal: Power Problems in VLSI Circuit Testing. VDAT 2012: 393-405

Vishwani D. Agrawal: Keynote Talk: A History of the VLSI Design Conference. VLSI Design 2012: 1-2

Priyadharshini Shanmugasundaram, Vishwani D. Agrawal: Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. VLSI Design 2012: 448-453

Lixing Zhao, Vishwani D. Agrawal: Net diagnosis using stuck-at and transition fault models. VTS 2012: 221-226

Suraj Sindia, Vishwani D. Agrawal: Towards spatial fault resilience in array processors. VTS 2012: 288-293

Vishwani D. Agrawal, Srimat T. Chakradhar (Eds.): 25th International Conference on VLSI Design, VLSID 2012, Hyderabad, India, January 7-11, 2012. IEEE 2012, isbn 978-1-4673-0438-2

Vishwani D. Agrawal: Editorial. J. Electronic Testing 27(1): 1-2 (2011)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 27(2): 95 (2011)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 27(3): 219 (2011)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 27(4): 425-426 (2011)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 27(5): 579 (2011)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 27(6): 681-682 (2011)

Kyungseok Kim, Vishwani D. Agrawal: Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. J. Low Power Electronics 7(4): 460-470 (2011)

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium 2011: 371-376

Yu Zhang, Vishwani D. Agrawal: Reduced complexity test generation algorithms for transition fault diagnosis. ICCD 2011: 96-101

Kyungseok Kim, Vishwani D. Agrawal: Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. ISQED 2011: 689-694

Kyungseok Kim, Vishwani D. Agrawal: True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. VLSI Design 2011: 292-297

Suraj Sindia, Vishwani D. Agrawal, Virendra Singh: Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS 2011: 64-69

Priyadharshini Shanmugasundaram, Vishwani D. Agrawal: Dynamic scan clock control for test time reduction maintaining peak power limit. VTS 2011: 248-253

Vishwani D. Agrawal: Editorial. J. Electronic Testing 26(1): 1-2 (2010)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 26(3): 293 (2010)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 26(4): 401 (2010)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 26(5): 495 (2010)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 26(6): 595-596 (2010)

Yu Zhang, Vishwani D. Agrawal: A diagnostic test generation system and a coverage metric. European Test Symposium 2010: 254

Fan Wang, Vishwani D. Agrawal: Soft error rate determination for nanoscale sequential logic. ISQED 2010: 225-230

Yu Zhang, Vishwani D. Agrawal: A diagnostic test generation system. ITC 2010: 360-368

Suraj Sindia, Virendra Singh, Vishwani D. Agrawal: Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design 2010: 288-293

Nitin Yogi, Vishwani D. Agrawal: Application of signal and noise theory to digital VLSI testing. VTS 2010: 215-220

Vishwani D. Agrawal: Editorial. J. Electronic Testing 25(1): 1 (2009)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 25(4-5): 209 (2009)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 25(6): 285 (2009)

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. VLSI Syst. 17(10): 1534-1545 (2009)

Suraj Sindia, Virendra Singh, Vishwani D. Agrawal: Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium 2009: 63-68

Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal: On Minimization of Peak Power for Scan Circuit during Test. European Test Symposium 2009: 25-30

Mohammed Ashfaq Shukoor, Vishwani D. Agrawal: A Two Phase Approach for Minimal Diagnostic Test Set Generation. European Test Symposium 2009: 115-120

Suraj Sindia, Virendra Singh, Vishwani D. Agrawal: Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI 2009: 69-74

Wei Jiang, Vishwani D. Agrawal: Designing Variation-tolerance in Mixed-signal Components of a System-on-chip. ISCAS 2009: 2313-2316

Jins D. Alexander, Vishwani D. Agrawal: Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. ISVLSI 2009: 127-132

Fan Wang, Vishwani D. Agrawal: Soft Error Rates with Inertial and Logical Masking. VLSI Design 2009: 459-464

Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal: Output Hazard-Free Transition Delay Fault Test Generation. VTS 2009: 97-102

Vishwani D. Agrawal: Editorial. J. Electronic Testing 24(1-3): 1 (2008)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 24(4): 321 (2008)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 24(5): 421 (2008)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 24(6): 505-506 (2008)

Vishwani D. Agrawal: A tutorial on test power. ISLPED 2008: 237-238

Wei Jiang, Vishwani D. Agrawal: Built-in Self-Calibration of On-chip DAC and ADC. ITC 2008: 1-10

Fan Wang, Vishwani D. Agrawal: Single Event Upset: An Embedded Tutorial. VLSI Design 2008: 429-434

Yuanlin Lu, Vishwani D. Agrawal: Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. VLSI Design 2008: 527-532

Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal: Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS 2008: 329-335

Vishwani D. Agrawal: Editorial. J. Electronic Testing 23(1): 5 (2007)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 23(2-3): 111 (2007)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 23(5): 369 (2007)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 23(6): 465 (2007)

Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal: Graphical I_DDQ Signatures Reduce Defect Level and Yield Loss. IEEE Trans. VLSI Syst. 15(11): 1245-1255 (2007)

Soumitra Bose, Vishwani D. Agrawal: Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. ITC 2007: 1-10

Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal: Delay fault simulation with bounded gate delay mode. ITC 2007: 1-10

Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal: SPARTAN: a spectral and information theoretic approach to partial-scan. ITC 2007: 1-10

Yuanlin Lu, Vishwani D. Agrawal: Statistical Leakage and Timing Optimization for Submicron Process Variation. VLSI Design 2007: 439-444

Nitin Yogi, Vishwani D. Agrawal: Spectral RTL Test Generation for Microprocessors. VLSI Design 2007: 473-478

Kalyana R. Kantipudi, Vishwani D. Agrawal: A Reduced Complexity Algorithm for Minimizing N-Detect Tests. VLSI Design 2007: 492-497

Soumitra Bose, Vishwani D. Agrawal: Delay Test Quality Evaluation Using Bounded Gate Delays. VTS 2007: 23-28

Vishwani D. Agrawal: Editorial. J. Electronic Testing 22(1): 5 (2006)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 22(2): 111 (2006)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 22(4-6): 307 (2006)

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electronics 2(1): 121-128 (2006)

Yuanlin Lu, Vishwani D. Agrawal: CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. J. Low Power Electronics 2(3): 378-387 (2006)

Fei Hu, Vishwani D. Agrawal: Input-specific dynamic power optimization for VLSI circuits. ISLPED 2006: 232-237

Soumitra Bose, Vishwani D. Agrawal: Fault Coverage Estimation for Non-Random Functional Input Sequences. ITC 2006: 1-10

Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram: Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS 2006: 88-93

Vishwani D. Agrawal: Editorial. J. Electronic Testing 21(1): 5 (2005)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 21(2): 111 (2005)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 21(3): 199 (2005)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 21(5): 459 (2005)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 21(6): 567 (2005)

Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja: Combinational automatic test pattern generation for acyclic sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 948-956 (2005)

Vishwani D. Agrawal, Alok S. Doshi: Concurrent Test Generation. Asian Test Symposium 2005: 294-299

Raja K. K. R. Sandireddy, Vishwani D. Agrawal: Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. DATE 2005: 1014-1019

Fei Hu, Vishwani D. Agrawal: Dual-transition glitch filtering in probabilistic waveform power estimation. ACM Great Lakes Symposium on VLSI 2005: 357-360

Fei Hu, Vishwani D. Agrawal: Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. ICCD 2005: 366-372

Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh: A random access scans architecture to reduce hardware overhead. ITC 2005: 9

Yuanlin Lu, Vishwani D. Agrawal: Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for V_th Assignment and Path Balancing. PATMOS 2005: 217-226

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS 2005: 436-445

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Variable Input Delay CMOS Logic for Low Power Design. VLSI Design 2005: 598-605

Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell: Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. VLSI Design 2005: 723-729

Vishwani D. Agrawal: 1985 to 1987: My years with D&T. IEEE Design & Test of Computers 21(3): 173-174 (2004)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 20(1): 5-6 (2004)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 20(2): 127 (2004)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 20(3): 219 (2004)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 20(4): 327 (2004)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 20(5): 459 (2004)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 20(6): 571 (2004)

Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell: A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. J. Comput. Sci. Technol. 19(6): 955-964 (2004)

Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal: On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. ITC 2004: 617-626

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: A Tuturial on the Emerging Nanotechnology Devices. VLSI Design 2004: 343-360

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design 2004: 1035-1040

Vishwani D. Agrawal: Editorial. J. Electronic Testing 19(1): 5 (2003)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 19(2): 95 (2003)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 19(3): 219 (2003)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 19(4): 363 (2003)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 19(6): 607 (2003)

Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1104-1113 (2003)

Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre: Fault Collapsing via Functional Dominance. ITC 2003: 274-280

Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja: Exclusive Test and its Applications to Fault Diagnosis. VLSI Design 2003: 143-148

Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell: A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. VLSI Design 2003: 149-154

Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal: New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. VLSI Design 2003: 353-360

Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design 2003: 527-532

Vishwani D. Agrawal: Editorial. J. Electronic Testing 18(1): 5 (2002)

Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: State and Fault Information for Compaction-Based Test Generation. J. Electronic Testing 18(1): 63-72 (2002)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 18(2): 103-104 (2002)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 18(3): 255 (2002)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 18(4-5): 359 (2002)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 18(6): 567-568 (2002)

Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell: A New Transitive Closure Algorithm with Application to Redundancy Identification. DELTA 2002: 496-500

Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal: Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ITC 2002: 375-383

A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre: A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. ITC 2002: 391-397

Vishwani D. Agrawal, Michael L. Bushnell: Electronic Testing for SOC Designers (Tutorial Abstract). VLSI Design 2002: 20

Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja: Multiple Faults: Modeling, Simulation and Test. VLSI Design 2002: 592-597

Vishwani D. Agrawal: Editorial. J. Electronic Testing 17(2): 79 (2001)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 17(3-4): 203 (2001)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 17(5): 367 (2001)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 17(6): 455 (2001)

Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Efficient spectral techniques for sequential ATPG. DATE 2001: 204-208

Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja: Combinational test generation for various classes of acyclic sequential circuits. ITC 2001: 1078-1087

Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal: Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. VLSI Design 2001: 143-148

Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. VTS 2001: 163-168

Vishwani D. Agrawal: Editorial. J. Electronic Testing 16(1-2): 5 (2000)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 16(3): 163 (2000)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 16(4): 315 (2000)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 16(5): 403-404 (2000)

Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi: False-Path Removal Using Delay Fault Simulation. J. Electronic Testing 16(5): 463-476 (2000)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 16(6): 571 (2000)

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 8(2): 223-228 (2000)

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Improving path delay testability of sequential circuits. IEEE Trans. VLSI Syst. 8(6): 736-741 (2000)

Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal: A testability metric for path delay faults and its application. ASP-DAC 2000: 593-598

Vishwani D. Agrawal, Kwang-Ting Cheng: Testing in the Fourth Dimension. Asian Test Symposium 2000: 2-

Kwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-

Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Compaction-based test generation using state and fault information. Asian Test Symposium 2000: 159-164

José T. de Sousa, Vishwani D. Agrawal: Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. DATE 2000: 640-644

Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. ITC 2000: 940-949

Vishwani D. Agrawal: Choice of Tests for Logic Verification and Equivalence Checking. VLSI Design 2000: 306-311

Vishwani D. Agrawal: Editorial. J. Electronic Testing 14(1-2): 7 (1999)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 14(3): 187-188 (1999)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 15(1-2): 5 (1999)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 15(3): 215 (1999)

Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal: A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. Great Lakes Symposium on VLSI 1999: 300-

Vishwani D. Agrawal: Panel: Increasing test coverage in a VLSI desgin course. ITC 1999: 1131

Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss: Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design 1999: 434-439

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: A Test Generator for Segment Delay Faults. VLSI Design 1999: 484-491

Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell: A Complete Characterization of Path Delay Faults through Stuck-at Faults. VLSI Design 1999: 492-497

Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. VTS 1999: 182-188

Vishwani D. Agrawal: Editorial. Design Autom. for Emb. Sys. 3(2-3): 115-116 (1998)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 12(1-2): 5 (1998)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 12(3): 167 (1998)

Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas: Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. J. Electronic Testing 12(3): 239-254 (1998)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 13(1): 5 (1998)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 13(2): 75 (1998)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 13(3): 219 (1998)

Vishwani D. Agrawal: Design of mixed-signal systems for testability. Integration 26(1-2): 141-150 (1998)

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers 47(8): 829-846 (1998)

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: The path-status graph with application to delay fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 324-332 (1998)

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 873-876 (1998)

Marwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell: False-Path Removal Using Delay Fault Simulation. Asian Test Symposium 1998: 82-87

Vishwani D. Agrawal, Sharad C. Seth: Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI 1998: 307-312

Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu: A non-enumerative path delay fault simulator for sequential circuits. ITC 1998: 934-943

Pramit Chavda, James Jacob, Vishwani D. Agrawal: Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221

Ananta K. Majhi, Vishwani D. Agrawal: Mixed-Signal Test. VLSI Design 1998: 285-288

Ananta K. Majhi, Vishwani D. Agrawal: Tutorial: Delay Fault Models and Coverage. VLSI Design 1998: 364-369

Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal: Path Delay Testing: Variable-Clock Versus Rated-Clock. VLSI Design 1998: 470-475

Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell: On Delay-Untestable Paths and Stuck-Fault Redundancy. VTS 1998: 194-199

Vishwani D. Agrawal: Editorial. J. Electronic Testing 10(1-2): 5 (1997)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 10(3): 171 (1997)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 11(1): 5 (1997)

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. J. Electronic Testing 11(1): 55-67 (1997)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 11(2): 107 (1997)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 11(3): 195 (1997)

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel: Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 759-762 (1997)

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: On variable clock methods for path delay testing of sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1237-1249 (1997)

Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal: Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1370-1377 (1997)

Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal: Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Syst. 5(2): 175-185 (1997)

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Fast identification of untestable delay faults using implications. ICCAD 1997: 642-647

Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski: Algorithms for Switch Level Delay Fault Simulation. ITC 1997: 982-991

Tapan J. Chakraborty, Vishwani D. Agrawal: Effective Path Selection for Delay Fault Testing of Sequential Circuits. ITC 1997: 998-1003

Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal: Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. VLSI Design 1997: 88-94

Vishwani D. Agrawal: Low-Power Design by Hazard Filtering. VLSI Design 1997: 193-197

James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal: Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. VLSI Design 1997: 514-515

Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian: Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457

Vishwani D. Agrawal: 1995 Asian Test Symposium carves a niche. IEEE Design & Test of Computers 13(2): 3- (1996)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 8(2): 111 (1996)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 9(1-2): 5 (1996)

Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Functional test generation for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 831-843 (1996)

Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin: Redundancy Identification Using Transitive Closure. Asian Test Symposium 1996: 4-9

Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal: Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: SIGMA: a simulator for segment delay faults. ICCAD 1996: 502-508

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. ITC 1996: 276-285

Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani: Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC 1996: 757-766

Vishwani D. Agrawal: Science, Technology, and the Indian Society. VLSI Design 1996: 6-9

Tapan J. Chakraborty, Vishwani D. Agrawal: Design for high-speed testability of stuck-at faults. VLSI Design 1996: 53-56

Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas: Statistical path delay fault coverage estimation for synchronous sequential circuits. VLSI Design 1996: 290-295

Vishwani D. Agrawal, David Lee: Characteristic polynomial method for verification and test of combinational circuits. VLSI Design 1996: 341-342

Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: On test coverage of path delay faults. VLSI Design 1996: 418-421

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Improving accuracy in path delay fault coverage estimation. VLSI Design 1996: 422-425

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Parallel concurrent path-delay fault simulation using single-input change patterns. VLSI Design 1996: 426-431

Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Segment delay faults: a new fault model. VTS 1996: 32-41

Vishwani D. Agrawal: Editorial. J. Electronic Testing 6(1): 5-6 (1995)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 6(2): 147 (1995)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 6(3): 263 (1995)

Vishwani D. Agrawal: Editorial - Special issue on partial scan design. J. Electronic Testing 7(1-2): 5-6 (1995)

Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An exact algorithm for selecting partial scan flip-flops. J. Electronic Testing 7(1-2): 83-93 (1995)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 7(3): 143 (1995)

Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal: Test Generation for Path Delay Faults Using Binary Decision Diagrams. IEEE Trans. Computers 44(3): 434-447 (1995)

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell: Fault coverage estimation by test vector sampling. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 590-596 (1995)

Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal: Energy models for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 728-739 (1995)

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: Test function embedding algorithms with application to interconnected finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1115-1127 (1995)

Vishwani D. Agrawal, Srimat T. Chakradhar: Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1155-1160 (1995)

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A partition and resynthesis approach to testable design of large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1268-1276 (1995)

Vishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri: Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-

Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell: Functional test generation for path delay faults. Asian Test Symposium 1995: 339-345

Soumitra Bose, Vishwani D. Agrawal: Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium 1995: 353-

James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal: An adaptive distributed algorithm for sequential circuit test generation. EURO-DAC 1995: 236-241

Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. ITC 1995: 139-148

Vishwani D. Agrawal, Tapan J. Chakraborty: High-Performance Circuit Testing with Slow-Speed Testers. ITC 1995: 302-310

James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal: An asynchronous algorithm for sequential circuit test generation on a network of workstations. VLSI Design 1995: 36-41

Tapan J. Chakraborty, Vishwani D. Agrawal: Robust testing for stuck-at faults. VLSI Design 1995: 42-46

Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Functional test generation for non-scan sequential circuits. VLSI Design 1995: 47-52

Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell: Statistical methods for delay fault coverage analysis. VLSI Design 1995: 166-170

Tapan J. Chakraborty, Vishwani D. Agrawal: Simulation of at-speed tests for stuck-at faults. VTS 1995: 216-220

Ernst G. Ulrich, Vishwani D. Agrawal, Jack H. Arabian: Concurrent and comparative discrete event simulation. Kluwer 1994, isbn 978-0-7923-9411-2, pp. I-XIII, 1-186

Vishwani D. Agrawal: Editorial. J. Electronic Testing 5(1): 5 (1994)

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Energy minimization and design for testability. J. Electronic Testing 5(1): 57-66 (1994)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 5(2-3): 127 (1994)

Vishwani D. Agrawal: A tale of two designs: the cheapest and the most economic. J. Electronic Testing 5(2-3): 131-135 (1994)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 5(4): 317 (1994)

Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An Exact Algorithm for Selecting Partial Scan Flip-Flops. DAC 1994: 81-86

Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal: An Efficient Path Delay Fault Coverage Estimator. DAC 1994: 516-521

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Test Function Architecture for Interconnected Finite State Machines. VLSI Design 1994: 113-116

Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal: Power Constraint Scheduling of Tests. VLSI Design 1994: 271-274

P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal: An Improved Deductive Fault Simulator. VLSI Design 1994: 307-310

Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell: FACTS: fault coverage estimation by test vector sampling. VTS 1994: 266-271

Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth: Generating Tests for Delay Faults in Nonscan Circuits. IEEE Design & Test of Computers 10(1): 20-28 (1993)

Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja: A Tutorial on Built-in Self-Test. I. Principles. IEEE Design & Test of Computers 10(1): 73-82 (1993)

Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja: A Tutorial on Built-In Self-Test, Part 2: Applications. IEEE Design & Test of Computers 10(2): 69-77 (1993)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 4(1): 5 (1993)

Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite state machine synthesis with fault tolerant test function. J. Electronic Testing 4(1): 57-69 (1993)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 4(2): 123 (1993)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 4(3): 199 (1993)

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: The optimistic update theorem for path delay testing in sequential circuits. J. Electronic Testing 4(3): 285-290 (1993)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 4(4): 295 (1993)

Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler: A transitive closure algorithm for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1015-1028 (1993)

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 1(4): 453-461 (1993)

D. Das, Sharad C. Seth, Vishwani D. Agrawal: Accurate computation of field reject ratio based on fault latency. IEEE Trans. VLSI Syst. 1(4): 537-545 (1993)

Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo: Sequential Circuit Test Generation on a Distributed System. DAC 1993: 107-111

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Design for Testability for Path Delay faults in Sequential Circuits. DAC 1993: 453-457

Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo: Test Pattern Generation for Sequential Circuits on a Network of Workstations. HPDC 1993: 114-120

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Generation of Compact Delay Tests by Multiple-Path Activation. ITC 1993: 714-723

Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Synthesis Approach to Design for Testability. ITC 1993: 754-763

Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: A Path Delay Fault Simulator for Sequential Circuits. VLSI Design 1993: 269-274

Vishwani D. Agrawal: Editorial. J. Electronic Testing 3(2): 105 (1992)

Ernst G. Ulrich, Karen Lentz, Jack H. Arabian, Michael Gustin, Vishwani D. Agrawal, Pier Luca Montessoro: The Comparative and Concurrent Simulation of discrete-event experiments. J. Electronic Testing 3(2): 107-118 (1992)

James Jacob, Vishwani D. Agrawal: Multiple fault detection in two-level multi-output circuits. J. Electronic Testing 3(2): 171-173 (1992)

Kwang-Ting Cheng, Vishwani D. Agrawal: Initializability Consideration in Sequential Machine Synthesis. IEEE Trans. Computers 41(3): 374-379 (1992)

Vishwani D. Agrawal, Srimat T. Chakradhar: Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 3(6): 739-746 (1992)

Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal: Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. DAC 1992: 159-164

Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC 1992: 165-172

Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite State Machine Synthesis with Fault Tolerant Test Function. DAC 1992: 562-567

Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Finite State Machine Testing Based on Growth and Dissappearance Faults. FTCS 1992: 238-245

Srimat T. Chakradhar, Vishwani D. Agrawal: A Transitive Closure Based Algorithm for Test Generation. DAC 1991: 353-358

Vishwani D. Agrawal: Design and Test-The Two Sides of a Coin. ICCD 1991: 12

Joan Villoldo, Prathima Agrawal, Vishwani D. Agrawal: Stafan Algorithms for MOS Circuits. ICCD 1991: 56-59

Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal: Estimating the Quality of Manufactured Digital Sequential Circuits. ITC 1991: 210-217

Vishwani D. Agrawal, Hatsuyoshi Kato: Fault Sampling Revisited. IEEE Design & Test of Computers 7(4): 32-35 (1990)

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong: Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Design & Test of Computers 7(5): 54-57 (1990)

Vishwani D. Agrawal: Editorial. J. Electronic Testing 1(2): 101 (1990)

Vishwani D. Agrawal, Kwang-Ting Cheng: Finite state machine synthesis with embedded test function. J. Electronic Testing 1(3): 221-228 (1990)

Kwang-Ting Cheng, Vishwani D. Agrawal: A Partial Scan Method for Sequential Circuits with Feedback. IEEE Trans. Computers 39(4): 544-549 (1990)

Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat: A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers 39(4): 582-586 (1990)

Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh: A Simulation-Based Method for Generating Tests for Sequential Circuits. IEEE Trans. Computers 39(12): 1456-1463 (1990)

Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal: Toward massively parallel automatic test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 981-994 (1990)

Vishwani D. Agrawal, Kwang-Ting Cheng: Test Function Specification in Synthesis. DAC 1990: 235-240

Kwang-Ting Cheng, Vishwani D. Agrawal: An Entropy Measure for the Complexity of Multi-Output Boolean Functions. DAC 1990: 302-305

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Automatic Test Generation Using Quadratic 0-1 Programming. DAC 1990: 654-659

Vishwani D. Agrawal, Kwang-Ting Cheng: An architecture for synthesis of testable finite state machines. EURO-DAC 1990: 612-616

Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Polynomial time solvable fault detection problems. FTCS 1990: 56-63

Vishwani D. Agrawal, Srimat T. Chakradhar: Logic Simulation and Parallel Processing. ICCAD 1990: 496-499

Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal: An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC 1990: 712-720

Vishwani D. Agrawal, Srimat T. Chakradhar: Performance estimation in a massively parallel system. SC 1990: 306-313

Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal: A directed search method for test generation using a concurrent simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 131-138 (1989)

Kwang-Ting Cheng, Vishwani D. Agrawal: An economical scan design for sequential logic test generation. FTCS 1989: 28-35

Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, R. Tutundjian: Fault Simulation in a Pipelined Multiprocessor System. ITC 1989: 727-734

Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal: Contest: A Concurrent Test Generator for Sequential Circuits. DAC 1988: 84-89

Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh: A sequential circuit test generation using threshold-value simulation. FTCS 1988: 24-29

Vishwani D. Agrawal, M. Ray Mercer: Deterministic Versus Random Testing. ITC 1986: 718

Sunil K. Jain, Vishwani D. Agrawal: Modeling and Test Generation Algorithms for MOS Circuits. IEEE Trans. Computers 34(5): 426-433 (1985)

Vishwani D. Agrawal, Samuel H. C. Poon: VLSI design process. ACM Conference on Computer Science 1985: 74-78

Prathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas: Multiple output minimization. DAC 1985: 674-680

Vishwani D. Agrawal: STAFAN Takes a Middle Course. ITC 1985: 796

Sharad C. Seth, Vishwani D. Agrawal: Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 123-126 (1984)

Sunil K. Jain, Vishwani D. Agrawal: STAFAN: An alternative to fault simulation. DAC 1984: 18-23

Alfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel: Chip layout optimization using critical path weighting. DAC 1984: 133-136

Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain: A gate level model for CMOS combinational logic circuits with application to fault detection. DAC 1984: 504-509

Vishwani D. Agrawal: Will Testability Analysis Replace Fault Simulation ? ITC 1984: 718-718

Sunil K. Jain, Vishwani D. Agrawal: Test generation for MOS circuits using D-algorithm. DAC 1983: 64-70

Vishwani D. Agrawal: Synchronous path analysis in MOS circuit simulator. DAC 1982: 629-635

Vishwani D. Agrawal, M. Ray Mercer: Testability Measures : What Do They Tell Us ? ITC 1982: 391-399

Vishwani D. Agrawal: An Information Theoretic Approach to Digital Fault Testing. IEEE Trans. Computers 30(8): 582-587 (1981)

Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal: LSI product quality and fault coverage. DAC 1981: 196-203

M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman: Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC 1981: 561-565

Vishwani D. Agrawal, Ajoy K. Bose, Patrick Kozak, Hao N. Nham, Ernesto Pacas-Skewes: A mixed-mode simulator. DAC 1980: 618-625

Vishwani D. Agrawal: Author's Reply. IEEE Trans. Computers 28(8): 581 (1979)

Vishwani D. Agrawal: Comments on ``An Approach to Highly Integrated Computer-Maintained Cellular Arrays''. IEEE Trans. Computers 28(9): 691-693 (1979)

Vishwani D. Agrawal: When to Use Random Testing. IEEE Trans. Computers 27(11): 1054-1055 (1978)

Prathima Agrawal, Vishwani D. Agrawal: On Monte Carlo Testing of Logic Tree Networks. IEEE Trans. Computers 25(6): 664-667 (1976)

Prathima Agrawal, Vishwani D. Agrawal: Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks. IEEE Trans. Computers 24(7): 691-695 (1975)