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Gil-Cho Ahn
2010 – today
- 2012
[c5]Yong-Sik Kwak, Kwang-Soo Kim, Gil-Cho Ahn: A 1.8 V 89.2 dB delta-sigma adc for sensor interface with on-chip reference. ISCAS 2012: 520-523- 2011
- [j4]Byeong-Woo Koo, Seung-Jae Park, Gil-Cho Ahn, Seung-Hoon Lee: A Single Amplifier-Based 12-bit 100 MS/s 1 V 19 mW 0.13 µm CMOS ADC with Various Power and Area Minimized Circuit Techniques. IEICE Transactions 94-C(8): 1282-1288 (2011)
- [j3]Chang-Seob Shin, Gil-Cho Ahn: A 10-bit 100-MS/s Dual-Channel Pipelined ADC Using Dynamic Memory Effect Cancellation Technique. IEEE Trans. on Circuits and Systems 58-II(5): 274-278 (2011)
- [c4]Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-Ju Kim, Kwang-Soo Kim, Seung-Hoon Lee, Gil-Cho Ahn: A 6.25 MHz BW 8-OSR fifth-order single-stage sigma-delta ADC. ISCAS 2011: 1117-1120
- 2010
- [j2]Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, Seung-Hoon Lee: A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp. J. Solid-State Circuits 45(3): 620-628 (2010)
- [c3]Xicheng Jiang, Jungwoo Song, Todd Brooks, Jianlong Chen, Vinay Chandrasekhar, Felix Cheung, Sherif Galal, Darwin Cheung, Gil-Cho Ahn, Madhulatha Bonu: A 10mW stereo audio CODEC in 0.13µm CMOS. ISSCC 2010: 82-83
2000 – 2009
- 2009
- [j1]Seung-Hoon Lee, Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn: A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration. IEEE Trans. on Circuits and Systems 56-I(5): 894-901 (2009)
- [c2]Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, Byeong-Ha Park: A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers. CICC 2009: 271-274
- 2004
- [c1]Min Gyu Kim, Gil-Cho Ahn, Un-Ku Moon: An improved algorithmic ADC clocking scheme. ISCAS (1) 2004: 589-592
Coauthor Index
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last updated on 2012-12-02 22:17 CET by the dblp team