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 | 2013 | |
|---|---|---|
| c45 |      | Cuong Pham-Quoc, Jan Heisswolf, Stephan Werner, Zaid Al-Ars, Jürgen Becker, Koen Bertels: Hybrid interconnect design for heterogeneous hardware accelerators. DATE 2013: 843-846 |
| c44 | | Hamid Mushtaq, Zaid Al-Ars, Koen Bertels: Efficient software-based fault tolerance approach on multicore platforms. DATE 2013: 921-926 |
| 2012 | ||
| c43 | | Hamid Mushtaq, Zaid Al-Ars, Koen Bertels: A user-level library for fault tolerance on shared memory multicore systems. DDECS 2012: 266-269 |
| c42 | | Cuong Pham-Quoc, Zaid Al-Ars, Koen Bertels: Rule-based data communication optimization using quantitative communication profiling. FPT 2012: 104-108 |
| c41 | | Cuong Pham-Quoc, Zaid Al-Ars, Koen Bertels: A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems. ReConFig 2012: 1-6 |
| c40 | | Hamid Mushtaq, Zaid Al-Ars, Koen Bertels: DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems. SC Companion 2012: 721-730 |
| 2011 | ||
| c39 | | Said Hamdioui, Venkataraman Krishnaswami, Ijeoma Sandra Irobi, Zaid Al-Ars: A New Test Paradigm for Semiconductor Memories in the Nano-Era. Asian Test Symposium 2011: 347-352 |
| c38 | | Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Claude Thibeault: Testing for Parasitic Memory Effect in SRAMs. Asian Test Symposium 2011: 407-412 |
| c37 | | Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell: Influence of parasitic memory effect on single-cell faults in SRAMs. DDECS 2011: 159-162 |
| c36 | | Sandra Irobi, Zaid Al-Ars, Said Hamdioui: Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs. European Test Symposium 2011: 205 |
| 2010 | ||
| c35 | | Sandra Irobi, Zaid Al-Ars, Said Hamdioui: Detecting memory faults in the presence of bit line coupling in SRAM devices. ITC 2010: 437-446 |
| c34 | | Andreas Eckel, Paul Milbredt, Zaid Al-Ars, Stefan Schneele, Bart Vermeulen, György Csertán, Christoph Scheerer, Neeraj Suri, Abdelmajid Khelil, Gerhard Fohler: INDEXYS, a Logical Step beyond GENESYS. SAFECOMP 2010: 431-451 |
| c33 | | Sandra Irobi, Zaid Al-Ars, Said Hamdioui: Bit line coupling memory tests for single-cell fails in SRAMs. VTS 2010: 27-32 |
| 2009 | ||
| c32 | | A. J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars: New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults. Asian Test Symposium 2009: 391-396 |
| c31 | | Zaid Al-Ars, Said Hamdioui: Fault Diagnosis Using Test Primitives in Random Access Memories. Asian Test Symposium 2009: 403-408 |
| 2008 | ||
| j7 | | Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis: Test Set Development for Cache Memory in Modern Microprocessors. IEEE Trans. VLSI Syst. 16(6): 725-732 (2008) |
| c30 | | Zubair Nawaz, Zaid Al-Ars, Koen Bertels, Mudassir Shabbir: Acceleration of Smith-Waterman using Recursive Variable Expansion. DSD 2008: 915-922 |
| c29 | | Stefano Di Carlo, Paolo Prinetto, Alberto Scionti, Zaid Al-Ars: Automating defects simulation and fault modeling for SRAMs. HLDVT 2008: 169-176 |
| c28 | | Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georg Mueller: Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs. ITC 2008: 1-10 |
| 2007 | ||
| c27 |  | Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Manifestation of Precharge Faults in High Speed DRAM Devices. DDECS 2007: 179-184 |
| c26 | | Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero: PPM Reduction on Embedded Memories in System on Chip. European Test Symposium 2007: 85-90 |
| c25 | | Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev: Optimizing Test Length for Soft Faults in DRAM Devices. VTS 2007: 59-66 |
| 2006 | ||
| j6 | | Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Opens and Delay Faults in CMOS RAM Address Decoders. IEEE Trans. Computers 55(12): 1630-1639 (2006) |
| j5 | | Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi: Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2989-2996 (2006) |
| c24 | | Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Space of DRAM fault models and corresponding testing. DATE 2006: 1252-1257 |
| c23 | | Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath: DRAM-Specific Space of Memory Tests. ITC 2006: 1-10 |
| 2005 | ||
| c22 | | Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath: Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach. Asian Test Symposium 2005: 434-439 |
| c21 | | Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor: Framework for Fault Analysis and Test Generation in DRAMs. DATE 2005: 1020-1021 |
| 2004 | ||
| j4 | | Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Linked faults in random access memories: concept, fault models, test algorithms, and industrial results. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 737-757 (2004) |
| c20 | | Said Hamdioui, John Delos Reyes, Zaid Al-Ars: Evaluation of Intra-Word Faults in Word-Oriented RAMs. Asian Test Symposium 2004: 283-288 |
| c19 | | Zaid Al-Ars, A. J. van de Goor: Soft Faults and the Importance of Stresses in Memory Testing. DATE 2004: 1084-1091 |
| c18 | | A. J. van de Goor, Said Hamdioui, Zaid Al-Ars: The Effectiveness of the Scan Test and Its New Variants. MTDT 2004: 26-31 |
| c17 | | Zaid Al-Ars, Martin Herzog, Ivo Schanstra, A. J. van de Goor: Influence of Bit Line Twisting on the Faulty Behavior of DRAMs. MTDT 2004: 32-37 |
| c16 | | Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: Effects of Bit Line Coupling on the Faulty Behavior of DRAMs. VTS 2004: 117-122 |
| 2003 | ||
| j3 | | Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests. J. Electronic Testing 19(2): 195-205 (2003) |
| j2 | | Zaid Al-Ars, A. J. van de Goor: Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs. IEEE Trans. Computers 52(3): 293-309 (2003) |
| j1 | | Zaid Al-Ars, A. J. van de Goor: Test generation and optimization for DRAM cell defects using electrical simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 22(10): 1371-1384 (2003) |
| c15 | | Zaid Al-Ars, A. J. van de Goor: Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces. Asian Test Symposium 2003: 24-27 |
| c14 | | Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers: March SL: A Test For All Static Linked Memory Faults. Asian Test Symposium 2003: 372-377 |
| c13 | | Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: Optimizing Stresses for Testing DRAM Cell Defects Using Electrical Simulation. DATE 2003: 10484-10489 |
| c12 | | Zaid Al-Ars, A. J. van de Goor: Systematic Memory Test Generation for DRAM Defects Causing Two Floating Nodes. MTDT 2003: 27-32 |
| c11 | | Zaid Al-Ars, Said Hamdioui, A. J. van de Goor: A Fault Primitive Based Analysis of Linked Faults in RAMs. MTDT 2003: 33- |
| 2002 | ||
| c10 | | Zaid Al-Ars, A. J. van de Goor: DRAM Specific Approximation of the Faulty Behavior of Cell Defects. Asian Test Symposium 2002: 98-103 |
| c9 | | Zaid Al-Ars, A. J. van de Goor: Modeling Techniques and Tests for Partial Faults in Memory Devices. DATE 2002: 89-93 |
| c8 | | Said Hamdioui, Zaid Al-Ars, A. J. van de Goor: Testing Static and Dynamic Faults in Random Access Memories. VTS 2002: 395-400 |
| c7 | | Zaid Al-Ars, A. J. van de Goor: Approximating Infinite Dynamic Behavior for DRAM Cell Defects. VTS 2002: 401-406 |
| 2001 | ||
| c6 | | Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: A Memory Specific Notation for Fault Modeling. Asian Test Symposium 2001: 43- |
| c5 | | Zaid Al-Ars, A. J. van de Goor: Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs. DATE 2001: 496-503 |
| c4 | | Zaid Al-Ars, A. J. van de Goor, Jens Braun, Detlev Richter: Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs. ITC 2001: 783-792 |
| c3 | | Zaid Al-Ars, A. J. van de Goor: Transient Faults in DRAMs: Concepts, Analysis and Impact on Tests. MTDT 2001: 59-64 |
| 2000 | ||
| c2 | | Zaid Al-Ars, A. J. van de Goor: Impact of memory cell array bridges on the faulty behavior in embedded DRAMs. Asian Test Symposium 2000: 282-289 |
| c1 | | A. J. van de Goor, Zaid Al-Ars: Functional Memory Faults: A Formal Notation and a Taxonomy. VTS 2000: 281-290 |
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