David H. Albonesi

Mark J. Cianchetti, David H. Albonesi: A low-latency, high-throughput on-chip optical router architecture for future chip multiprocessors. JETC 7(2): 9 (2011)

Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo: A phase adaptive cache hierarchy for SMT processors. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 683-694 (2011)

Matthew A. Watkins, David H. Albonesi: ReMAP: A Reconfigurable Architecture for Chip Multiprocessors. IEEE Micro 31(1): 65-77 (2011)

David H. Albonesi: Future Directions in Computer Architecture Research. IEEE Micro 30(3): 5 (2010)

David H. Albonesi: Moving Forward. IEEE Micro 30(6): 4-5 (2010)

Jonathan A. Winter, David H. Albonesi, Christine A. Shoemaker: Scalable thread scheduling and global power management for heterogeneous many-core architectures. PACT 2010: 29-40

Matthew A. Watkins, David H. Albonesi: Dynamically managed multithreaded reconfigurable architectures for chip multiprocessors. PACT 2010: 41-52

Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo: Adaptive Cache Memories for SMT Processors. DSD 2010: 331-338

Matthew A. Watkins, David H. Albonesi: ReMAP: A Reconfigurable Heterogeneous Multicore Architecture. MICRO 2010: 497-508

David H. Albonesi: From the Editor in Chief: Welcome A-Board. IEEE Micro 29(5): 2-5 (2009)

Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi: Phastlane: a rapid transit optical routing network. ISCA 2009: 441-450

David H. Albonesi, Margaret Martonosi, David I. August, José F. Martínez (Eds.): 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA. ACM 2009, isbn 978-1-60558-798-1

David H. Albonesi: Changes Ahead. IEEE Micro 28(5): 4 (2008)

Jonathan A. Winter, David H. Albonesi: Addressing thermal nonuniformity in SMT workloads. TACO 5(1) (2008)

Jonathan A. Winter, David H. Albonesi: Scheduling algorithms for unpredictably heterogeneous CMP architectures. DSN 2008: 42-51

Matthew A. Watkins, Mark J. Cianchetti, David H. Albonesi: Shared reconfigurable architectures for CMPS. FPL 2008: 299-304

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman: Predictions of CMOS compatible on-chip optical interconnect. Integration 40(4): 434-446 (2007)

David H. Albonesi: Standing on Solid Ground. IEEE Micro 27(1): 5-6 (2007)

Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi: On-Chip Optical Technology in Future Bus-Based Multicore Designs. IEEE Micro 27(1): 56-66 (2007)

David H. Albonesi: Editor in Chief's Message: Truly "hot" chips - Do we still care? IEEE Micro 27(2): 4-5 (2007)

David H. Albonesi: More Hot Stuff. IEEE Micro 27(3): 4-5 (2007)

David H. Albonesi: Mixing It Up. IEEE Micro 27(4): 3-4 (2007)

David H. Albonesi: Productive and Healthy Debate. IEEE Micro 27(6): 6 (2007)

Sonia López, Steven G. Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares: Rate-Driven Control of Resizable Caches for Highly Threaded SMT Processors. PACT 2007: 416

Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares: Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. HiPEAC 2007: 136-150

Ali El-Moursy, R. Garg, David H. Albonesi, Sandhya Dwarkadas: Compatible phase co-scheduling on a CMP of multi-threaded processors. IPDPS 2006

YongKang Zhu, David H. Albonesi: Localized microarchitecture-level voltage management. ISCAS 2006

YongKang Zhu, David H. Albonesi: Synergistic temperature and energy management in GALS processor architectures. ISLPED 2006: 55-60

Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi: Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. MICRO 2006: 492-503

M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi: Power-Efficient Error Tolerance in Chip Multiprocessors. IEEE Micro 25(6): 60-70 (2005)

M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi: Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance. IEEE PACT 2005: 315-328

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi: Electrical and optical on-chip interconnects in scaled microprocessors. ISCAS (3) 2005: 2514-2517

YongKang Zhu, David H. Albonesi, Alper Buyuktosunoglu: A High Performance, Energy Efficient GALS ProcessorMicroarchitecture with Reduced Implementation Complexity. ISPASS 2005: 42-53

Ali El-Moursy, Rajeev Garg, David H. Albonesi, Sandhya Dwarkadas: Partitioning Multi-Threaded Processors with a Large Number of Threads. ISPASS 2005: 112-123

Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi: Predictions of CMOS compatible on-chip optical interconnect. SLIP 2005: 13-20

Wanli Liu, David H. Albonesi, John Gostomski, Lloyd Palum, Dave Hinterberger, Rick Wanzenried, Mark Indovina: An Evaluation of a Configurable Vliw Microarchitecture for Embedded Dsp Applications. Journal of Circuits, Systems, and Computers 13(6): 1321-1346 (2004)

David H. Albonesi: Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. IEEE Micro 24(6): 8-9 (2004)

YongKang Zhu, Grigorios Magklis, Michael L. Scott, Chen Ding, David H. Albonesi: The Energy Impact of Aggressive Loop Fusion. IEEE PACT 2004: 153-164

Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas: Hiding Synchronization Delays in a GALS Processor Microarchitecture. ASYNC 2004: 159-169

Steven G. Dropsho, Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott: Dynamically Trading Frequency for Complexity in a GALS Microprocessor. MICRO 2004: 157-168

David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster: Dynamically Tuning Processor Resources with Adaptive Processing. IEEE Computer 36(12): 49-58 (2003)

Pradip Bose, David H. Albonesi, Diana Marculescu: Guest Editors' Introduction: Power and Complexity Aware Design. IEEE Micro 23(5): 8-11 (2003)

Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott: Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor. IEEE Micro 23(6): 62-68 (2003)

Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas: A Dynamically Tunable Memory Hierarchy. IEEE Trans. Computers 52(10): 1243-1258 (2003)

Ali El-Moursy, David H. Albonesi: Front-End Policies for Improved Issue Efficiency in SMT Processors. HPCA 2003: 31-40

Lei Chen, Steve Dropsho, David H. Albonesi: Dynamic Data Dependence Tracking and its Application to Branch Prediction. HPCA 2003: 65-76

Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho: Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. ISCA 2003: 14-25

Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose: Energy Efficient Co-Adaptive Instruction Fetch and Issue. ISCA 2003: 147-156

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. ISCA 2003: 275-286

Steve Dropsho, Alper Buyuktosunoglu, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Greg Semeraro, Grigorios Magklis, Michael L. Scott: Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. IEEE PACT 2002: 141-152

Greg Semeraro, Grigorios Magklis, Rajeev Balasubramonian, David H. Albonesi, Sandhya Dwarkadas, Michael L. Scott: Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling. HPCA 2002: 29-42

Alper Buyuktosunoglu, David H. Albonesi, Pradip Bose, Peter W. Cook, Stanley Schuster: Tradeoffs in power-efficient issue queue design. ISLPED 2002: 184-189

Wael El-Essawy, David H. Albonesi, Balaram Sinharoy: A microarchitectural-level step-power analysis tool. ISLPED 2002: 263-266

Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman: Managing static leakage energy in microprocessor functional units. MICRO 2002: 321-332

Greg Semeraro, David H. Albonesi, Steve Dropsho, Grigorios Magklis, Sandhya Dwarkadas, Michael L. Scott: Dynamic frequency and voltage control for a multiple clock domain microarchitecture. MICRO 2002: 356-367

Pradip Bose, David Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, Sandhya Dwarkadas: Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. PACS 2002: 1-17

Alper Buyuktosunoglu, David H. Albonesi, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook: A circuit level implementation of an adaptive issue queue for power-aware microprocessors. ACM Great Lakes Symposium on VLSI 2001: 73-78

Brian W. Curran, Mary Gifaldi, Jason Martin, Alper Buyuktosunoglu, Martin Margala, David H. Albonesi: Low-Voltage 0, 25 µm CMOS Improved Power Adaptive Issue Queue for Embedded Microprocessors. VLSI-SOC 2001: 289-300

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Dynamically allocating processor resources between nearby and distant ILP. ISCA 2001: 26-37

Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi: Reducing the complexity of the register file in dynamic superscalar processors. MICRO 2001: 237-248

Bingxiong Xu, David H. Albonesi: Runtime Reconfiguration Techniques for Efficient General-Purpose Computation. IEEE Design & Test of Computers 17(1): 42-52 (2000)

David H. Albonesi: Selective Cache Ways: On-Demand Cache Resource Allocation. J. Instruction-Level Parallelism 2 (2000)

Rajeev Balasubramonian, David H. Albonesi, Alper Buyuktosunoglu, Sandhya Dwarkadas: Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. MICRO 2000: 245-257

Alper Buyuktosunoglu, Stanley Schuster, David Brooks, Pradip Bose, Peter W. Cook, David H. Albonesi: An Adaptive Issue Queue for Reduced Power at High Performance. PACS 2000: 25-39

David H. Albonesi, Israel Koren: STATS: A framework for microprocessor and system-level design space exploration. Journal of Systems Architecture 45(12-13): 1097-1110 (1999)

David H. Albonesi: An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures. VLSI 1999: 192-205

David H. Albonesi: Selective Cache Ways: On-Demand Cache Resource Allocation. MICRO 1999: 248-

David H. Albonesi: Dynamic IPC/Clock Rate Optimization. ISCA 1998: 282-292

David H. Albonesi, Israel Koren: Improving the Memory Bandwidth of Highly-Integrated, Wide-Issue, Microprocessor-Based Systems. IEEE PACT 1997: 126-135

David H. Albonesi, Israel Koren: A Mean Analysis Multiprocessor Model Incorporating Superscalar Processors and Latency Tolerating Techniques. International Journal of Parallel Programming 24(3): 235-264 (1996)

David H. Albonesi, Israel Koren: Tradeoffs in the Design of Single Chip Multiprocessors. IFIP PACT 1994: 25-34