Rajeev Alur

Rajeev Alur, Vojtech Forejt, Salar Moarref, Ashutosh Trivedi: Safe schedulability of bounded-rate multi-mode systems. HSCC 2013: 243-252

Rajeev Alur, Sampath Kannan, Kevin Tian, Yifei Yuan: On the Complexity of Shortest Path Problems on Discounted Cost Graphs. LATA 2013: 44-55

Rajeev Alur, Vojtech Forejt, Salar Moarref, Ashutosh Trivedi: Safe Schedulability of Bounded-Rate Multi-Mode Systems. CoRR abs/1302.0745 (2013)

Rajeev Alur, Mukund Raghothaman: Decision Problems for Additive Regular Functions. CoRR abs/1304.7029 (2013)

Orna Grumberg, Moshe Y. Vardi, Joseph Sifakis, Rajeev Alur: 2010 CAV award announcement. Formal Methods in System Design 40(2): 117-120 (2012)

Moshe Y. Vardi, Thomas A. Henzinger, Rajeev Alur, Marta Z. Kwiatkowska: 2011 CAV award announcement. Formal Methods in System Design 41(1): 1-2 (2012)

Truong Nghiem, George J. Pappas, Rajeev Alur, Antoine Girard: Time-Triggered Implementations of Dynamic Controllers. ACM Trans. Embedded Comput. Syst. 11(S2): 58 (2012)

Rajeev Alur, Pavol Cerný, Scott Weinstein: Algorithmic analysis of array-accessing programs. ACM Trans. Comput. Log. 13(3): 27 (2012)

Sela Mador-Haim, Luc Maranget, Susmit Sarkar, Kayvan Memarian, Jade Alglave, Scott Owens, Rajeev Alur, Milo M. K. Martin, Peter Sewell, Derek Williams: An Axiomatic Memory Model for POWER Multiprocessors. CAV 2012: 495-512

Rajeev Alur, Ashutosh Trivedi, Dominik Wojtczak: Optimal scheduling for constant-rate multi-mode systems. HSCC 2012: 75-84

Rajeev Alur, Loris D'Antoni: Streaming Tree Transducers. ICALP (2) 2012: 42-53

Rajeev Alur, Emmanuel Filiot, Ashutosh Trivedi: Regular Transformations of Infinite Strings. LICS 2012: 65-74

Zhihao Jiang, Miroslav Pajic, Salar Moarref, Rajeev Alur, Rahul Mangharam: Modeling and Verification of a Dual Chamber Implantable Pacemaker. TACAS 2012: 188-203

Rajeev Alur, Alessandro D'Innocenzo, Karl Henrik Johansson, George J. Pappas, Gera Weiss: Compositional Modeling and Analysis of Multi-Hop Control Networks. IEEE Trans. Automat. Contr. 56(10): 2345-2357 (2011)

Rajeev Alur, Swarat Chaudhuri, P. Madhusudan: Software model checking using languages of nested trees. ACM Trans. Program. Lang. Syst. 33(5): 15 (2011)

Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin: Litmus tests for comparing memory consistency models: how long do they need to be? DAC 2011: 504-509

Rajeev Alur, Ashutosh Trivedi: Relating average and discounted costs for quantitative analysis of timed systems. EMSOFT 2011: 165-174

Rajeev Alur: Formal verification of hybrid systems. EMSOFT 2011: 273-278

Rajeev Alur: Interfaces for Control Components. FORMATS 2011: 25

Rajeev Alur, Jyotirmoy V. Deshmukh: Nondeterministic Streaming String Transducers. ICALP (2) 2011: 1-20

Rajeev Alur, Pavol Cerný: Streaming transducers for algorithmic verification of single-pass list-processing programs. POPL 2011: 599-610

Rajeev Alur: Streaming String Transducers. WoLLIC 2011: 1

Rajeev Alur, Loris D'Antoni: Streaming Tree Transducers. CoRR abs/1104.2599 (2011)

Rajeev Alur, Loris D'Antoni, Jyotirmoy V. Deshmukh, Mukund Raghothaman, Yifei Yuan: Regular Functions, Cost Register Automata, and Generalized Min-Cost Problems. CoRR abs/1111.0670 (2011)

Wonhong Nam, Rajeev Alur: Active Learning of Plans for Safety and Reachability Goals With Partial Observability. IEEE Transactions on Systems, Man, and Cybernetics, Part B 40(2): 412-420 (2010)

Sela Mador-Haim, Rajeev Alur, Milo M. K. Martin: Generating Litmus Tests for Contrasting Memory Consistency Models. CAV 2010: 273-287

Pavol Cerný, Arjun Radhakrishna, Damien Zufferey, Swarat Chaudhuri, Rajeev Alur: Model Checking of Linearizability of Concurrent List Implementations. CAV 2010: 465-479

Rajeev Alur, Pavol Cerný: Expressiveness of streaming string transducers. FSTTCS 2010: 1-12

Aditya Kanade, Rajeev Alur, Sriram K. Rajamani, Ganesan Ramalingam: Representation dependence testing using program inversion. SIGSOFT FSE 2010: 277-286

Rajeev Alur, Swarat Chaudhuri: Temporal Reasoning for Procedural Programs. VMCAI 2010: 45-60

Rajeev Alur, Pavol Cerný: Algorithmic Verification of Single-Pass List Processing Programs. CoRR abs/1007.4958 (2010)

Rajeev Alur, P. Madhusudan: Adding nesting structure to words. J. ACM 56(3) (2009)

Alessandro D'Innocenzo, Gera Weiss, Rajeev Alur, Alf J. Isaksson, Karl Henrik Johansson, George J. Pappas: Scalable scheduling algorithms for wireless networked control systems. CASE 2009: 409-414

Pavol Cerný, Rajeev Alur: Automated Analysis of Java Methods for Confidentiality. CAV 2009: 173-187

Aditya Kanade, Rajeev Alur, Franjo Ivancic, S. Ramesh, Sriram Sankaranarayanan, K. C. Shashidhar: Generating and Analyzing Symbolic Traces of Simulink/Stateflow Models. CAV 2009: 430-445

Gera Weiss, Alessandro D'Innocenzo, Rajeev Alur, Karl Henrik Johansson, George J. Pappas: Robust stability of multi-hop control networks. CDC 2009: 2210-2215

Rajeev Alur, Pavol Cerný, Scott Weinstein: Algorithmic Analysis of Array-Accessing Programs. CSL 2009: 86-101

Rajeev Alur: Temporal Reasoning about Program Executions. FOSSACS 2009: 15

Rajeev Alur, Aldric Degorre, Oded Maler, Gera Weiss: On Omega-Languages Defined by Mean-Payoff Conditions. FOSSACS 2009: 333-347

Gera Weiss, Sebastian Fischmeister, Madhukar Anand, Rajeev Alur: Specification and Analysis of Network Resource Requirements of Control Systems. HSCC 2009: 381-395

Rajeev Alur, Alessandro D'Innocenzo, Karl Henrik Johansson, George J. Pappas, Gera Weiss: Modeling and Analysis of Multi-hop Control Networks. IEEE Real-Time and Embedded Technology and Applications Symposium 2009: 223-232

Rajeev Alur, George J. Pappas: Introduction. Formal Methods in System Design 32(1): 1 (2008)

Wonhong Nam, P. Madhusudan, Rajeev Alur: Automatic symbolic compositional verification by learning assumptions. Formal Methods in System Design 32(3): 207-234 (2008)

Rajeev Alur, Marcelo Arenas, Pablo Barceló, Kousha Etessami, Neil Immerman, Leonid Libkin: First-Order and Temporal Logics for Nested Words. Logical Methods in Computer Science 4(4) (2008)

Rajeev Alur: Marrying Words and Trees. AMAST 2008: 1

Rajeev Alur, Aditya Kanade, Gera Weiss: Ranking Automata and Games for Prioritized Requirements. CAV 2008: 240-253

Rajeev Alur, Aditya Kanade, S. Ramesh, K. C. Shashidhar: Symbolic analysis for improving simulation coverage of Simulink/Stateflow models. EMSOFT 2008: 89-98

Rajeev Alur, Gera Weiss: RTComposer: a framework for real-time components with scheduling interfaces. EMSOFT 2008: 159-168

Rajeev Alur, Gera Weiss: Regular Specifications of Resource Requirements for Embedded Control Software. IEEE Real-Time and Embedded Technology and Applications Symposium 2008: 159-168

Rajeev Alur: Model Checking: From Tools to Theory. 25 Years of Model Checking 2008: 89-106

Rajeev Alur, Marcelo Arenas, Pablo Barceló, Kousha Etessami, Neil Immerman, Leonid Libkin: First-Order and Temporal Logics for Nested Words. CoRR abs/0811.0537 (2008)

Rajeev Alur, Arun Chandrashekharapuram: Dispatch sequences for embedded control models. J. Comput. Syst. Sci. 73(2): 156-170 (2007)

Rajeev Alur: Marrying Words and Trees. CSR 2007: 5

Mikhail Bernadsky, Rajeev Alur: Symbolic Analysis for GSMP Models with One Stateful Clock. HSCC 2007: 90-103

Gera Weiss, Rajeev Alur: Automata Based Interfaces for Control and Scheduling. HSCC 2007: 601-613

Rajeev Alur, Marcelo Arenas, Pablo Barceló, Kousha Etessami, Neil Immerman, Leonid Libkin: First-Order and Temporal Logics for Nested Words. LICS 2007: 151-160

Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin: CheckFence: checking consistency of concurrent data types on relaxed memory models. PLDI 2007: 12-21

Rajeev Alur: Marrying words and trees. PODS 2007: 233-242

Swarat Chaudhuri, Rajeev Alur: Instrumenting C Programs with Nested Word Monitors. SPIN 2007: 279-283

Rajeev Alur, Pavol Cerný, Swarat Chaudhuri: Model Checking on Trees with Path Equivalences. TACAS 2007: 664-678

Rajeev Alur, Radu Grosu, Insup Lee, Oleg Sokolsky: Compositional modeling and refinement for hierarchical hybrid systems. J. Log. Algebr. Program. 68(1-2): 105-128 (2006)

Rajeev Alur, Salvatore La Torre, P. Madhusudan: Modular strategies for recursive game graphs. Theor. Comput. Sci. 354(2): 230-249 (2006)

Rajeev Alur, Thao Dang, Franjo Ivancic: Counterexample-guided predicate abstraction of hybrid systems. Theor. Comput. Sci. 354(2): 250-271 (2006)

Rajeev Alur, Thao Dang, Franjo Ivancic: Predicate abstraction for reachability analysis of hybrid systems. ACM Trans. Embedded Comput. Syst. 5(1): 152-199 (2006)

Wonhong Nam, Rajeev Alur: Learning-Based Symbolic Assume-Guarantee Reasoning with Automatic Decomposition. ATVA 2006: 170-185

Rajeev Alur, Swarat Chaudhuri, P. Madhusudan: Languages of Nested Trees. CAV 2006: 329-342

Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin: Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study. CAV 2006: 489-502

Rajeev Alur, P. Madhusudan: Adding Nesting Structure to Words. Developments in Language Theory 2006: 1-13

Truong Nghiem, George J. Pappas, Rajeev Alur, Antoine Girard: Time-triggered implementations of dynamic controllers. EMSOFT 2006: 2-11

Rajeev Alur, Swarat Chaudhuri: Branching Pushdown Tree Automata. FSTTCS 2006: 393-404

Rajeev Alur, Mikhail Bernadsky: Bounded Model Checking for GSMP Models of Stochastic Real-Time Systems. HSCC 2006: 19-33

Rajeev Alur, Pavol Cerný, Steve Zdancewic: Preserving Secrecy Under Refinement. ICALP (2) 2006: 107-118

Rajeev Alur: Games for formal design and verification of reactive systems. MEMOCODE 2006: 3

Rajeev Alur, Swarat Chaudhuri, P. Madhusudan: A fixpoint calculus for local and global program flows. POPL 2006: 153-165

Rajeev Alur, Kenneth L. McMillan, Doron Peled: Deciding Global Partial-Order Properties. Formal Methods in System Design 26(1): 7-25 (2005)

Rajeev Alur, P. Madhusudan, Wonhong Nam: Symbolic computational techniques for solving games. STTT 7(2): 118-128 (2005)

Rajeev Alur, Kousha Etessami, Mihalis Yannakakis: Realizability and verification of MSC graphs. Theor. Comput. Sci. 331(1): 97-114 (2005)

Rajeev Alur, Insup Lee: Preface. ACM Trans. Embedded Comput. Syst. 4(4): 707 (2005)

Rajeev Alur, Michael Benedikt, Kousha Etessami, Patrice Godefroid, Thomas W. Reps, Mihalis Yannakakis: Analysis of recursive state machines. ACM Trans. Program. Lang. Syst. 27(4): 786-818 (2005)

Rajeev Alur, P. Madhusudan, Wonhong Nam: Symbolic Compositional Verification by Learning Assumptions. CAV 2005: 548-562

Rajeev Alur: The Benefits of Exposing Calls and Returns. CONCUR 2005: 2-3

Rajeev Alur, Salvatore La Torre, P. Madhusudan: Perturbed Timed Automata. HSCC 2005: 70-85

Rajeev Alur, Viraj Kumar, P. Madhusudan, Mahesh Viswanathan: Congruences for Visibly Pushdown Languages. ICALP 2005: 1102-1114

Rajeev Alur, Pavol Cerný, P. Madhusudan, Wonhong Nam: Synthesis of interface specifications for Java classes. POPL 2005: 98-109

Rajeev Alur, Arun Chandrashekharapuram: Dispatch Sequences for Embedded Control Models. IEEE Real-Time and Embedded Technology and Applications Symposium 2005: 508-518

Hakan Yazarel, Antoine Girard, George J. Pappas, Rajeev Alur: Quantifying the Gap between Embedded Control Models and Time-Triggered Implementations. RTSS 2005: 111-120

Rajeev Alur, Swarat Chaudhuri, Kousha Etessami, P. Madhusudan: On-the-Fly Reachability and Cycle Detection for Recursive State Machines. TACAS 2005: 61-76

Sebastian Burckhardt, Rajeev Alur, Milo M. K. Martin: Verifying Safety of a Token Coherence Implementation by Parametric Compositional Refinement. VMCAI 2005: 130-145

Rajeev Alur: Trends and Challenges in Algorithmic Software Verification. VSTTE 2005: 245-250

Rajeev Alur, Sampath Kannan, Salvatore La Torre: Polyhedral Flows in Hybrid Automata. Formal Methods in System Design 24(3): 261-280 (2004)

Rajeev Alur, David Arney, Elsa L. Gunter, Insup Lee, Jaime Lee, Wonhong Nam, Frederick Pearce, Stephen Van Albert, Jiaxiang Zhou: Formal specifications and analysis of the computer-assisted resuscitation algorithm (CARA) Infusion Pump Control System. STTT 5(4): 308-319 (2004)

Rajeev Alur, Salvatore La Torre, George J. Pappas: Optimal paths in weighted timed automata. Theor. Comput. Sci. 318(3): 297-322 (2004)

Rajeev Alur, Salvatore La Torre: Deterministic generators and games for Ltl fragments. ACM Trans. Comput. Log. 5(1): 1-25 (2004)

Rajeev Alur, Radu Grosu: Modular refinement of hierarchic reactive machines. ACM Trans. Program. Lang. Syst. 26(2): 339-369 (2004)

Rajeev Alur: Games for Formal Design and Verification of Reactive Systems. ATVA 2004: 1

Michael McDougall, Rajeev Alur, Carl A. Gunter: A model-based approach to integrating security policies for embedded devices. EMSOFT 2004: 211-219

Zijiang Yang, Rajeev Alur: Variable Reuse for Efficient Image Computation. FMCAD 2004: 430-444

Mikhail Bernadsky, Raman Sharykin, Rajeev Alur: Structured Modeling of Concurrent Stochastic Hybrid Systems. FORMATS/FTRTFT 2004: 309-324

Rajeev Alur, Mikhail Bernadsky, P. Madhusudan: Optimal Reachability for Weighted Timed Games. ICALP 2004: 122-133

Rajeev Alur, P. Madhusudan: Decision Problems for Timed Automata: A Survey. SFM 2004: 1-24

Rajeev Alur, P. Madhusudan: Visibly pushdown languages. STOC 2004: 202-211

Rajeev Alur, Kousha Etessami, P. Madhusudan: A Temporal Logic of Nested Calls and Returns. TACAS 2004: 467-481

Rajeev Alur, Doron Peled (Eds.): Computer Aided Verification, 16th International Conference, CAV 2004, Boston, MA, USA, July 13-17, 2004, Proceedings. Lecture Notes in Computer Science 3114, Springer 2004, isbn 3-540-22342-8

Rajeev Alur, George J. Pappas (Eds.): Hybrid Systems: Computation and Control, 7th International Workshop, HSCC 2004, Philadelphia, PA, USA, March 25-27, 2004, Proceedings. Lecture Notes in Computer Science 2993, Springer 2004, isbn 3-540-21259-0

P. Madhusudan, Wonhong Nam, Rajeev Alur: Symbolic computational techniques for solving games. Electr. Notes Theor. Comput. Sci. 89(4): 578-592 (2003)

Rajeev Alur, Thao Dang, Joel M. Esposito, Yerang Hur, Franjo Ivancic, Vijay Kumar, Insup Lee, Pradyumna Mishra, George J. Pappas, Oleg Sokolsky: Hierarchical modeling and analysis of embedded systems. Proceedings of the IEEE 91(1): 11-28 (2003)

Rajeev Alur, Kousha Etessami, Mihalis Yannakakis: Inference of Message Sequence Charts. IEEE Trans. Software Eng. 29(7): 623-633 (2003)

Rajeev Alur: Formal Analysis of Hierarchical State Machines. Verification: Theory and Practice 2003: 42-66

Rajeev Alur, Salvatore La Torre, P. Madhusudan: Modular Strategies for Infinite Games on Recursive Graphs. CAV 2003: 67-79

Rajeev Alur, Swarat Chaudhuri, Kousha Etessami, Sudipto Guha, Mihalis Yannakakis: Compression of Partially Ordered Strings. CONCUR 2003: 42-56

Rajeev Alur, Salvatore La Torre, P. Madhusudan: Playing Games with Boxes and Diamonds. CONCUR 2003: 127-141

Rajeev Alur, Thao Dang, Franjo Ivancic: Progress on Reachability Analysis of Hybrid Systems Using Predicate Abstraction. HSCC 2003: 4-19

Rajeev Alur, Franjo Ivancic, Jesung Kim, Insup Lee, Oleg Sokolsky: Generating embedded software from hierarchical hybrid models. LCTES 2003: 171-182

Rajeev Alur, Thao Dang, Franjo Ivancic: Counter-Example Guided Predicate Abstraction of Hybrid Systems. TACAS 2003: 208-223

Rajeev Alur, Salvatore La Torre, P. Madhusudan: Modular Strategies for Recursive Game Graphs. TACAS 2003: 363-378

Rajeev Alur, Insup Lee (Eds.): Embedded Software, Third International Conference, EMSOFT 2003, Philadelphia, PA, USA, October 13-15, 2003, Proceedings. Lecture Notes in Computer Science 2855, Springer 2003, isbn 3-540-20223-4

Rafael B. Fierro, Aveek K. Das, John R. Spletzer, Joel M. Esposito, Vijay Kumar, James P. Ostrowski, George J. Pappas, Camillo J. Taylor, Yerang Hur, Rajeev Alur, Insup Lee, Gregory Z. Grudic, Ben Southall: A Framework and Architecture for Multi-Robot Coordination. I. J. Robotic Res. 21(10-11): 977-998 (2002)

Rajeev Alur, Thomas A. Henzinger, Orna Kupferman: Alternating-time temporal logic. J. ACM 49(5): 672-713 (2002)

Alwyn Goodloe, Michael McDougall, Carl A. Gunter, Rajeev Alur: Predictable programs in barcodes. CASES 2002: 298-303

Rajeev Alur, Michael McDougall, Zijiang Yang: Exploiting Behavioral Hierarchy for Efficient Model Checking. CAV 2002: 338-342

Rajeev Alur, Calin Belta, Franjo Ivancic, Vijay Kumar, Harvey Rubin, Jonathan Schug, Oleg Sokolsky, Jonathan Webb: Visual Programming for Modeling and Simulation of Biomolecular Regulatory Networks. HiPC 2002: 702-712

Rajeev Alur, Thao Dang, Franjo Ivancic: Reachability Analysis of Hybrid Systems via Predicate Abstraction. HSCC 2002: 35-48

Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani: Partial-Order Reduction in Symbolic State-Space Exploration. Formal Methods in System Design 18(2): 97-116 (2001)

Rajeev Alur, Thomas A. Henzinger: Introduction. Inf. Comput. 164(2): 233 (2001)

Rajeev Alur, Kousha Etessami, Salvatore La Torre, Doron Peled: Parametric temporal logic for "model measuring". ACM Trans. Comput. Log. 2(3): 388-407 (2001)

Rajeev Alur, Mihalis Yannakakis: Model checking of hierarchical state machines. ACM Trans. Program. Lang. Syst. 23(3): 273-303 (2001)

Rajeev Alur, Bow-Yaw Wang: Verifying Network Protocol Implementations by Symbolic Refinement Checking. CAV 2001: 169-181

Rajeev Alur, Kousha Etessami, Mihalis Yannakakis: Analysis of Recursive State Machines. CAV 2001: 207-220

M. Oliver Möller, Rajeev Alur: Heuristics for Hierarchical Partitioning with Application to Model Checking. CHARME 2001: 71-85

Rajeev Alur, Thao Dang, Joel M. Esposito, Rafael B. Fierro, Yerang Hur, Franjo Ivancic, Vijay Kumar, Insup Lee, Pradyumna Mishra, George J. Pappas, Oleg Sokolsky: Hierarchical Hybrid Modeling of Embedded Systems. EMSOFT 2001: 14-31

Rajeev Alur, Calin Belta, Franjo Ivancic: Hybrid Modeling and Simulation of Biomolecular Networks. HSCC 2001: 19-32

Rajeev Alur, Radu Grosu, Insup Lee, Oleg Sokolsky: Compositional Refinement for Hierarchical Hybrid Systems. HSCC 2001: 33-48

Rajeev Alur, Salvatore La Torre, George J. Pappas: Optimal Paths in Weighted Timed Automata. HSCC 2001: 49-62

Rajeev Alur, Kousha Etessami, Mihalis Yannakakis: Realizability and Verification of MSC Graphs. ICALP 2001: 797-808

Rajeev Alur, Luca de Alfaro, Radu Grosu, Thomas A. Henzinger, M. Kang, Christoph M. Kirsch, Rupak Majumdar, Freddy Y. C. Mang, Bow-Yaw Wang: JMOCHA: A Model Checking Tool that Exploits Design Structure. ICSE 2001: 835-836

Rajeev Alur, Radu Grosu: Shared Variables Interaction Diagrams. ASE 2001: 281-288

Rajeev Alur, Salvatore La Torre: Deterministic Generators and Games for LTL Fragments. LICS 2001: 291-300

Rajeev Alur, Kenneth L. McMillan, Doron Peled: Model-Checking of Correctness Conditions for Concurrent Objects. Inf. Comput. 160(1-2): 167-188 (2000)

Rajeev Alur: Computer-aided verification of reactive systems. ACM SIGSOFT Software Engineering Notes 25(1): 32-33 (2000)

Rajeev Alur, Radu Grosu, Michael McDougall: Efficient Reachability Analysis of Hierarchical Reactive Machines. CAV 2000: 280-295

Rajeev Alur: Exploiting Hierarchical Structure for Efficient Formal Verification. CONCUR 2000: 66-68

Rajeev Alur, Radu Grosu, Bow-Yaw Wang: Automated Refinement Checking for Asynchronous Processes. FMCAD 2000: 55-72

Rajeev Alur, Radu Grosu, Yerang Hur, Vijay Kumar, Insup Lee: Modular Specification of Hybrid Systems in CHARON. HSCC 2000: 6-19

Rajeev Alur, Kousha Etessami, Mihalis Yannakakis: Inference of message sequence charts. ICSE 2000: 304-313

Rajeev Alur, Aveek K. Das, Joel M. Esposito, Rafael B. Fierro, Gregory Z. Grudic, Yerang Hur, Vijay Kumar, Insup Lee, J. P. Lee, James P. Ostrowski, George J. Pappas, Ben Southall, John R. Spletzer, Camillo J. Taylor: A Framework and Architecture for Multirobot Coordination. ISER 2000: 303-312

Rajeev Alur, Radu Grosu: Modular Refinement of Hierarchic Reactive Machines. POPL 2000: 390-402

Rajeev Alur, Thomas A. Henzinger: Introduction. Formal Methods in System Design 14(3): 235 (1999)

Rajeev Alur, Thomas A. Henzinger: Introduction. Formal Methods in System Design 15(1): 5 (1999)

Rajeev Alur, Thomas A. Henzinger: Reactive Modules. Formal Methods in System Design 15(1): 7-48 (1999)

Rajeev Alur, Doron Peled: Undecidability of Partial Order Logics. Inf. Process. Lett. 69(3): 137-143 (1999)

Rajeev Alur, Limor Fix, Thomas A. Henzinger: Event-Clock Automata: A Determinizable Class of Timed Automata. Theor. Comput. Sci. 211(1-2): 253-273 (1999)

Rajeev Alur: Timed Automata. CAV 1999: 8-22

Rajeev Alur, Luca de Alfaro, Thomas A. Henzinger, Freddy Y. C. Mang: Automating Modular Verification. CONCUR 1999: 82-97

Rajeev Alur, Bow-Yaw Wang: ``Next'' Heuristic for On-the-Fly Model Checking. CONCUR 1999: 98-113

Rajeev Alur, Mihalis Yannakakis: Model Checking of Message Sequence Charts. CONCUR 1999: 114-129

Rajeev Alur, Joel M. Esposito, M. Kim, Vijay Kumar, Insup Lee: Formal Modeling and Analysis of Hybrid Systems: A Case Study in Multi-robot Coordination. World Congress on Formal Methods 1999: 212-232

Rajeev Alur, Sampath Kannan, Salvatore La Torre: Polyhedral Flows in Hybrid Automata. HSCC 1999: 5-18

Rajeev Alur, Kousha Etessami, Salvatore La Torre, Doron Peled: Parametric Temporal Logic for "Model Measuring". ICALP 1999: 159-168

Rajeev Alur, Sampath Kannan, Mihalis Yannakakis: Communicating Hierarchical State Machines. ICALP 1999: 169-178

Rajeev Alur, Thomas A. Henzinger: Finitary Fairness. ACM Trans. Program. Lang. Syst. 20(6): 1171-1194 (1998)

Rajeev Alur, Thomas A. Henzinger, Freddy Y. C. Mang, Shaz Qadeer, Sriram K. Rajamani, Serdar Tasiran: MOCHA: Modularity in Model Checking. CAV 1998: 521-525

Rajeev Alur, Thomas A. Henzinger, Orna Kupferman, Moshe Y. Vardi: Alternating Refinement Relations. CONCUR 1998: 163-178

Allen D. Malony, Rajeev Alur: Performance Evaluation and Prediction. Euro-Par 1998: 191-192

Rajeev Alur: Efficient Formal Verification of Hierarchical Descriptions. FSTTCS 1998: 269

Rajeev Alur, Kenneth L. McMillan, Doron Peled: Deciding Global Partial-Order Properties. ICALP 1998: 41-52

Rajeev Alur, Robert P. Kurshan, Mahesh Viswanathan: Membership Questions for Timed and Hybrid Automata. RTSS 1998: 254-263

Rajeev Alur, Mihalis Yannakakis: Model Checking of Hierarchical State Machines. SIGSOFT FSE 1998: 175-188

Rajeev Alur, Thomas A. Henzinger, Sriram K. Rajamani: Symbolic Exploration of transition Hierarchies. TACAS 1998: 330-344

Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger: Computing Accumulated Delays in Real-time Systems. Formal Methods in System Design 11(2): 137-155 (1997)

Rajeev Alur, Hagit Attiya, Gadi Taubenfeld: Time-Adaptive Algorithms for Synchronization. SIAM J. Comput. 26(2): 539-556 (1997)

Rajeev Alur, Thomas A. Henzinger: Real-Time System = Discrete System + Clock Variables. STTT 1(1-2): 86-109 (1997)

Rajeev Alur, Robert K. Brayton, Thomas A. Henzinger, Shaz Qadeer, Sriram K. Rajamani: Partial-Order Reduction in Symbolic State Space Exploration. CAV 1997: 340-351

Rajeev Alur, Thomas A. Henzinger, Orna Kupferman: Alternating-Time Temporal Logic. COMPOS 1997: 23-60

Rajeev Alur, Thomas A. Henzinger: Modularity for Timed and Hybrid Systems. CONCUR 1997: 74-88

Rajeev Alur, Thomas A. Henzinger, Orna Kupferman: Alternating-time Temporal Logic. FOCS 1997: 100-109

Rajeev Alur, Lalita Jategaonkar Jagadeesan, Joseph J. Kott, James Von Olnhausen: Model-Checking of Real-Time Systems: A Telecommunications Application (Experience Report). ICSE 1997: 514-524

Rajeev Alur: Next Steps in Formal Verification. ACM Comput. Surv. 28(4es): 115 (1996)

Rajeev Alur, Gadi Taubenfeld: Fast Timing-Based Algorithms. Distributed Computing 10(1): 1-10 (1996)

Rajeev Alur, Gadi Taubenfeld: Contention-Free Complexity of Shared Memory Algorithms. Inf. Comput. 126(1): 62-73 (1996)

Rajeev Alur, Tomás Feder, Thomas A. Henzinger: The Benefits of Relaxing Punctuality. J. ACM 43(1): 116-146 (1996)

Rajeev Alur, Gerard J. Holzmann, Doron Peled: An Analyzer for Message Sequence Charts. Software - Concepts and Tools 17(2): 70-77 (1996)

Rajeev Alur, Thomas A. Henzinger, Pei-Hsin Ho: Automatic Symbolic Verification of Embedded Systems. IEEE Trans. Software Eng. 22(3): 181-201 (1996)

Serdar Tasiran, Rajeev Alur, Robert P. Kurshan, Robert K. Brayton: Verifying Abstractions of Timed Systems. CONCUR 1996: 546-562

Rajeev Alur, Thomas A. Henzinger: Reactive Modules. LICS 1996: 207-218

Rajeev Alur, Kenneth L. McMillan, Doron Peled: Model-Checking of Correctness Conditions for Concurrent Objects. LICS 1996: 219-228

Rajeev Alur, Gerard J. Holzmann, Doron Peled: An Analyser for Mesage Sequence Charts. TACAS 1996: 35-48

Rajeev Alur, Thomas A. Henzinger (Eds.): Computer Aided Verification, 8th International Conference, CAV '96, New Brunswick, NJ, USA, July 31 - August 3, 1996, Proceedings. Lecture Notes in Computer Science 1102, Springer 1996, isbn 3-540-61474-5

Rajeev Alur, Thomas A. Henzinger, Eduardo D. Sontag (Eds.): Hybrid Systems III: Verification and Control, Proceedings of the DIMACS/SYCON Workshop, October 22-25, 1995, Ruttgers University, New Brunswick, NJ, USA. Lecture Notes in Computer Science 1066, Springer 1996, isbn 3-540-61155-X

Rajeev Alur, Alon Itai, Robert P. Kurshan, Mihalis Yannakakis: Timing Verification by Successive Approximation. Inf. Comput. 118(1): 142-157 (1995)

Rajeev Alur, Costas Courcoubetis, Nicolas Halbwachs, Thomas A. Henzinger, Pei-Hsin Ho, Xavier Nicollin, Alfredo Olivero, Joseph Sifakis, Sergio Yovine: The Algorithmic Analysis of Hybrid Systems. Theor. Comput. Sci. 138(1): 3-34 (1995)

Rajeev Alur, Thomas A. Henzinger: Local Liveness for Compositional Modeling of Fair Reactive Systems. CAV 1995: 166-179

Rajeev Alur, Robert P. Kurshan: Timing Analysis in COSPAN. Hybrid Systems 1995: 220-231

Rajeev Alur, Doron Peled, Wojciech Penczek: Model-Checking of Causality Properties. LICS 1995: 90-100

Rajeev Alur, Costas Courcoubetis, Mihalis Yannakakis: Distinguishing tests for nondeterministic and probabilistic machines. STOC 1995: 363-372

Rajeev Alur, Thomas A. Henzinger: A Really Temporal Logic. J. ACM 41(1): 181-204 (1994)

Rajeev Alur, David L. Dill: A Theory of Timed Automata. Theor. Comput. Sci. 126(2): 183-235 (1994)

Rajeev Alur, Limor Fix, Thomas A. Henzinger: A Determinizable Class of Timed Automata. CAV 1994: 1-13

Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger: The Observational Power of Clocks. CONCUR 1994: 162-177

Rajeev Alur, Thomas A. Henzinger: Finitary Fairness. LICS 1994: 52-61

Rajeev Alur, Gadi Taubenfeld: Contention-free Complexity of Shared Memory Algorithms. PODC 1994: 61-70

Rajeev Alur, Hagit Attiya, Gadi Taubenfeld: Time-adaptive algorithms for synchronization. STOC 1994: 800-809

Rajeev Alur, Costas Courcoubetis, David L. Dill: Model-Checking in Dense Real-time. Inf. Comput. 104(1): 2-34 (1993)

Rajeev Alur, Thomas A. Henzinger: Real-Time Logics: Complexity and Expressiveness. Inf. Comput. 104(1): 35-77 (1993)

Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger: Computing Accumulated Delays in Real-time Systems. CAV 1993: 181-193

Rajeev Alur, Thomas A. Henzinger, Pei-Hsin Ho: Automatic Symbolic Verification of Embedded Systems. RTSS 1993: 2-11

Rajeev Alur, Gadi Taubenfeld: How to Share an Object: A Fast Timing-Based Solution. SPDP 1993: 470-477

Rajeev Alur, Thomas A. Henzinger, Moshe Y. Vardi: Parametric real-time reasoning. STOC 1993: 592-601

Rajeev Alur, Alon Itai, Robert P. Kurshan, Mihalis Yannakakis: Timing Verification by Successive Approximation. CAV 1992: 137-150

Rajeev Alur, Costas Courcoubetis, Nicolas Halbwachs, David L. Dill, Howard Wong-Toi: Minimization of Timed Transition Systems. CONCUR 1992: 340-354

Rajeev Alur, Thomas A. Henzinger: Back to the Future: Towards a Theory of Timed Regular Languages. FOCS 1992: 177-186

Rajeev Alur, Costas Courcoubetis, Thomas A. Henzinger, Pei-Hsin Ho: Hybrid Automata: An Algorithmic Approach to the Specification and Verification of Hybrid Systems. Hybrid Systems 1992: 209-229

Rajeev Alur, Gadi Taubenfeld: Results about Fast Mutual Exclusion. RTSS 1992: 12-21

Rajeev Alur, Costas Courcoubetis, David L. Dill, Nicolas Halbwachs, Howard Wong-Toi: An implementation of three algorithms for timing verification based on automata emptiness. RTSS 1992: 157-166

Rajeev Alur, Costas Courcoubetis, David L. Dill: Model-Checking for Probabilistic Real-Time Systems (Extended Abstract). ICALP 1991: 115-126

Rajeev Alur, Tomás Feder, Thomas A. Henzinger: The Benefits of Relaxing Punctuality. PODC 1991: 139-152

Rajeev Alur, Costas Courcoubetis, David L. Dill: Verifying Automata Specifications of Probabilistic Real-time Systems. REX Workshop 1991: 28-44

Rajeev Alur, David L. Dill: The Theory of Timed Automata. REX Workshop 1991: 45-73

Rajeev Alur, Thomas A. Henzinger: Logics and Models of Real Time: A Survey. REX Workshop 1991: 74-106

Rajeev Alur, David L. Dill: Automata For Modeling Real-Time Systems. ICALP 1990: 322-335

Rajeev Alur, Thomas A. Henzinger: Real-time Logics: Complexity and Expressiveness. LICS 1990: 390-401

Rajeev Alur, Costas Courcoubetis, David L. Dill: Model-Checking for Real-Time Systems. LICS 1990: 414-425

Rajeev Alur, Thomas A. Henzinger: A Really Temporal Logic. FOCS 1989: 164-169