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 | 2013 | |
|---|---|---|
| j49 |      | Hiroshi Nakamura, Weihan Wang, Yuya Ohta, Kimiyoshi Usami, Hideharu Amano, Masaaki Kondo, Mitaro Namiki: Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. IEICE Transactions 96-C(4): 404-412 (2013) |
| c195 | | Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, Hideharu Amano: An FPGA Acceleration for the Kd-tree Search in Photon Mapping. ARC 2013: 25-36 |
| c194 | | Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano: A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 |
| 2012 | ||
| j48 | | |
| j47 | | Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: Partial Reconfiguration of Flux Limiter Functions in MUSCL Scheme Using FPGA. IEICE Transactions 95-D(10): 2369-2376 (2012) |
| j46 | | |
| c193 | | Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: Cost Effective Implementation of Flux Limiter Functions Using Partial Reconfiguration. ARC 2012: 215-226 |
| c192 | | Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano: Vertical Link On/Off Control Methods for Wireless 3-D NoCs. ARCS 2012: 212-224 |
| c191 | | Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412 |
| c190 | | Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: Reconfigurable out-of-order mechanism generator for unstructured grid computation in computational fluid dynamics. FPL 2012: 136-142 |
| c189 | | Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 |
| c188 | | Amila Akagic, Hideharu Amano: Performance analysis of fully-adaptable CRC accelerators on an FPGA. FPL 2012: 575-578 |
| c187 | | Amila Akagic, Hideharu Amano: A study of adaptable co-processors for Cyclic Redundancy Check on an FPGA. FPT 2012: 119-124 |
| c186 | | Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura: Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 |
| c185 | | Takaaki Miyajima, David Thomas, Hideharu Amano: A Domain Specific Language and Toolchain for OpenCV Runtime Binary Acceleration Using GPU. ICNC 2012: 175-181 |
| c184 | | Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova: A case for random shortcut topologies for HPC interconnects. ISCA 2012: 177-188 |
| c183 | | Hideharu Amano: Castle of Chips: A New Chip Stacking Structure with Wireless Inductive Coupling for Large Scale 3-D Multicore Systems. NBiS 2012: 820-825 |
| c182 | | Toru Katagiri, Kazuei Hironaka, Hideharu Amano: Extension of Memory Controller Equipped with MuCCRA-3-DP: Dynamically Reconfigurable Processor Array. NBiS 2012: 826-831 |
| c181 | | Mohamad Sofian Abu Talip, Takayuki Akamine, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: Dynamically reconfigurable flux limiter functions in MUSCL scheme. ReCoSoC 2012: 1-7 |
| c180 | | Ryuichi Sakamoto, Mikiko Sato, Yusuke Koizumi, Hideharu Amano, Mitaro Namiki: An OpenCL Runtime Library for Embedded Multi-Core Accelerator. RTCSA 2012: 419-422 |
| 2011 | ||
| j45 | | Lei Zhao, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano: A Leakage Efficient Data TLB Design for Embedded Processors. IEICE Transactions 94-D(1): 51-59 (2011) |
| j44 | | Zhao Lei, Hui Xu, Daisuke Ikebuchi, Tetsuya Sunata, Mitaro Namiki, Hideharu Amano: A Leakage Efficient Instruction TLB Design for Embedded Processors. IEICE Transactions 94-D(8): 1565-1574 (2011) |
| j43 | | Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano: Iterative Synthesis Methods Estimating Programmable-Wire Congestion in a Dynamically Reconfigurable Processor. IEICE Transactions 94-A(12): 2619-2627 (2011) |
| j42 | | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano: An analytical network performance model for SIMD processor CSX600 interconnects. Journal of Systems Architecture - Embedded Systems Design 57(1): 146-159 (2011) |
| j41 | | Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo: Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. IEEE Micro 31(6): 6-18 (2011) |
| j40 | | Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: An implementation of out-of-order execution system for acceleration of computational fluid dynamics on FPGAs. SIGARCH Computer Architecture News 39(4): 50-55 (2011) |
| j39 | | Amila Akagic, Hideharu Amano: High speed CRC with 64-bit generator polynomial on an FPGA. SIGARCH Computer Architecture News 39(4): 72-77 (2011) |
| j38 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011) |
| j37 | | Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. on CAD of Integrated Circuits and Systems 30(4): 520-533 (2011) |
| j36 | | Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano: A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet. IEEE Trans. Parallel Distrib. Syst. 22(2): 217-230 (2011) |
| c179 | | Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami: Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction. ARC 2011: 230-241 |
| c178 | | Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo: Geyser-2: The second prototype CPU with fine-grained run-time power gating. ASP-DAC 2011: 87-88 |
| c177 | | Kazuei Hironaka, Nobuaki Ozaki, Hideharu Amano: The realtime image processing demonstration with CMA-1: An ultra low-power reconfigurable accelerator. FPT 2011: 1-4 |
| c176 | | Masayuki Kimura, Kazuei Hironaka, Hideharu Amano: Reducing power for dynamically reconfigurable processor array by reducing number of reconfigurations. FPT 2011: 1-8 |
| c175 | | Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo: Cool Mega-Array: A highly energy efficient reconfigurable accelerator. FPT 2011: 1-8 |
| c174 | | Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano: Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC 2011: 50-57 |
| c173 | | Akihiro Shitara, Tetsuya Nakahama, Masahiro Yamada, Toshiaki Kamata, Yuri Nishikawa, Masato Yoshimi, Hideharu Amano: Vegeta: An Implementation and Evaluation of Development-Support Middleware on Multiple OpenCL Platform. ICNC 2011: 141-147 |
| c172 | | Tetsuya Nakahama, Masahiro Yamada, Masato Yoshimi, Hideharu Amano: Proposal of Auto MPI Expansion Tool for Cell Broadband Engine Cluster. ICNC 2011: 166-172 |
| c171 | | Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura: On-chip detection methodology for break-even time of power gated function units. ISLPED 2011: 241-246 |
| c170 | | Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano: A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS 2011: 49-56 |
| c169 | | Kazuei Hironaka, Hideharu Amano: Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. ReConFig 2011: 404-409 |
| c168 | | Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano: A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) 2011: 106-108 |
| 2010 | ||
| j35 | | Hirokazu Morishita, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: Implementation and evaluation of an arithmetic pipeline on FLOPS-2D: multi-FPGA system. SIGARCH Computer Architecture News 38(4): 8-13 (2010) |
| c167 | | Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer: A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster. ARC 2010: 372-381 |
| c166 | | Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo: Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. ASP-DAC 2010: 369-370 |
| c165 | | Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano: MuCCRA-3: a low power dynamically reconfigurable processor array. ASP-DAC 2010: 377-378 |
| c164 | | Takao Toi, Takumi Okamoto, Toru Awashima, Kazutoshi Wakabayashi, Hideharu Amano: Wire congestion aware synthesis for a dynamically reconfigurable processor. FPT 2010: 300-303 |
| c163 | | Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano: Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping. FPT 2010: 349-352 |
| c162 | | Yui Ogawa, Tomonori Ooya, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri: A datapath classification method for FPGA-based scientific application accelerator systems. FPT 2010: 441-444 |
| c161 | | Zhao Lei, Hui Xu, Daisuke Ikebuchi, Hideharu Amano, Tetsuya Sunata, Mitaro Namiki: Reducing instruction TLB's leakage power consumption for embedded processors. Green Computing Conference 2010: 477-484 |
| c160 | | Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: Adaptive power gating for function units in a microprocessor. ISQED 2010: 29-37 |
| c159 | | José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS 2010: 218-227 |
| c158 | | Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS 2010: 431-438 |
| c157 | | Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68 |
| e3 | | Phaophak Sirisuk, Fearghal Morgan, Tarek A. El-Ghazawi, Hideharu Amano (Eds.): Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings. Lecture Notes in Computer Science 5992, Springer 2010, isbn 978-3-642-12132-6 |
| 2009 | ||
| j34 | | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 92-D(4): 575-583 (2009) |
| j33 | | Iver Stubdal, Arda Karaduman, Hideharu Amano: Code Compression with Split Echo Instructions. IEICE Transactions 92-D(9): 1650-1656 (2009) |
| j32 | | Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano: Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distrib. Syst. 20(8): 1126-1141 (2009) |
| j31 | | |
| c156 | | Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri: Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator. ARC 2009: 368-373 |
| c155 | | Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano: Cache Controller Design on Ultra Low Leakage Embedded Processors. ARCS 2009: 171-182 |
| c154 |  | |
| c153 | | Toru Sano, Yoshiki Saito, Hideharu Amano: Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors. ERSA 2009: 112-118 |
| c152 | | Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano: A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array. ERSA 2009: 283-286 |
| c151 | | Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano: MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11 |
| c150 | | Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano: Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors. FPL 2009: 530-533 |
| c149 | | Kenta Inakagata, Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: Modularizing flux limiter functions for a Computational Fluid Dynamics accelerator on FPGAs. FPL 2009: 654-657 |
| c148 | | Tomonori Ooya, Hideki Yamada, Tomoya Ishimori, Yuichiro Shibata, Yasunori Osana, Kiyoshi Oguri, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano: Configuring area and performance: Empirical evaluation on an FPGA-based biochemical simulator. FPL 2009: 679-682 |
| c147 | | Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano: Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. FPT 2009: 104-111 |
| c146 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378 |
| c145 | | José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano: Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops 2009: 499-506 |
| c144 | | Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano: An on/off link activation method for low-power ethernet in PC clusters. IPDPS 2009: 1-11 |
| c143 | | Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano: Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS 2009: 1-8 |
| c142 | | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano: Performance Analysis of ClearSpeed's CSX600 Interconnects. ISPA 2009: 203-210 |
| c141 | | José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano: An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA 2009: 289-295 |
| c140 | | Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri: A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA. ReConFig 2009: 125-130 |
| c139 | | Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura: Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. VLSI Design 2009: 381-386 |
| 2008 | ||
| j30 | | Vu Manh Tuan, Hideharu Amano: A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. IEICE Transactions 91-D(9): 2312-2322 (2008) |
| j29 | | Vasutan Tunbunheng, Hideharu Amano: A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays. IEICE Transactions 91-D(11): 2655-2665 (2008) |
| j28 | | Vu Manh Tuan, Hideharu Amano: A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processors. IEICE Transactions 91-D(12): 2793-2803 (2008) |
| c138 | | Vu Manh Tuan, Hideharu Amano: A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor. ARC 2008: 171-182 |
| c137 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang: Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60 |
| c136 | | Vu Manh Tuan, Hideharu Amano: A Method for Capturing State Data on Dynamically Reconfigurable Processors. ERSA 2008: 208-214 |
| c135 | | Masaru Kato, Yohei Hasegawa, Hideharu Amano: Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor with Directly Interconnected PEs. ERSA 2008: 215-221 |
| c134 | | Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano: Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. FPL 2008: 215-220 |
| c133 | | Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi: A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274 |
| c132 | | Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano: Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL 2008: 305-310 |
| c131 | | Masato Yoshimi, Yuri Nishikawa, Yasunori Osana, Akira Funahashi, Yuichiro Shibata, Hideki Yamada, Noriko Hiroi, Hiroaki Kitano, Hideharu Amano: Practical implementation of a network-based stochastic biochemical simulation system on an FPGA. FPL 2008: 663-666 |
| c130 | | Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano: Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors. FPT 2008: 137-144 |
| c129 | | Hirokazu Morishita, Yasunori Osana, Naoyuki Fujita, Hideharu Amano: Exploiting memory hierarchy for a Computational Fluid Dynamics accelerator on FPGAs. FPT 2008: 193-200 |
| c128 | | Yoshiki Saito, Tomoaki Shirai, Takuro Nakamura, Takashi Nishimura, Yohei Hasegawa, Satoshi Tsutsumi, Toshihiro Kashima, Mitsutaka Nakata, Seidai Takeda, Kimiyoshi Usami, Hideharu Amano: Leakage power reduction for coarse grained dynamically reconfigurable processor arrays with fine grained Power Gating technique. FPT 2008: 329-332 |
| c127 | | Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura: A fine-grain dynamic sleep control scheme in MIPS R3000. ICCD 2008: 612-617 |
| c126 | | Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano: Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288 |
| c125 | | Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston: A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22 |
| c124 | | Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32 |
| c123 | | Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano: Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor. ReConFig 2008: 247-252 |
| 2007 | ||
| j27 | | Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano: Data Multicasting Procedure for Increasing Configuration Speed of Coarse Grain Reconfigurable Devices. IEICE Transactions 90-D(2): 473-481 (2007) |
| j26 | | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 90-D(12): 1914-1922 (2007) |
| j25 | | Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano: An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. IEEE Trans. Parallel Distrib. Syst. 18(3): 320-333 (2007) |
| j24 | | Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hiroaki Nishi, Junji Yamamoto, Noboru Tanabe, Tomohiro Kudoh, Hideharu Amano: Martini: A Network Interface Controller Chip for High Performance Computing with Distributed PCs. IEEE Trans. Parallel Distrib. Syst. 18(9): 1282-1295 (2007) |
| c122 | | Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka: Implementation and Evaluation of a High Speed License Plate Recognition System on an FPGA. CIT 2007: 567-572 |
| c121 | | Vu Manh Tuan, Yohei Hasegawa, Hideharu Amano: Performance Analysis of Multi-process Execution Model on Dynamically Reconfigurable Processor. ERSA 2007: 203-206 |
| c120 | | Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano: FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method. FPL 2007: 254-259 |
| c119 | | Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388 |
| c118 | | Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka: A High Speed License Plate Recognition System on an FPGA. FPL 2007: 554-557 |
| c117 | | Yohei Hasegawa, Hideharu Amano: Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays. FPL 2007: 796-799 |
| c116 | | Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri: A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator. FPL 2007: 808-811 |
| c115 | | Masato Yoshimi, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Hideki Yamada, Hiroaki Kitano, Hideharu Amano: A Framework for Implementing a Network-Based Stochastic Biochemical Simulator on an FPGA. FPT 2007: 193-200 |
| c114 | | Satoshi Tsutsumi, Vasutan Tunbunheng, Yohei Hasegawa, Adepu Parimala, Takuro Nakamura, Takashi Nishimura, Hideharu Amano: Overwrite Configuration Technique in Multicast Configuration Scheme for Dynamically Reconfigurable Processor Arrays. FPT 2007: 273-276 |
| c113 | | Vu Manh Tuan, Hideharu Amano: A Mapping Method for Multi-Process Execution on Dynamically Reconfigurable Processors. FPT 2007: 357-360 |
| c112 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75 |
| c111 | | Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano: Performance Improvement Methodology for ClearSpeed's CSX600. ICPP 2007: 77 |
| c110 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10 |
| c109 | | Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano: Performance evaluation on low-latency communication mechanism of DIMMnet-2. Parallel and Distributed Computing and Networks 2007: 57-62 |
| c108 | | Atsushi Ohta, Yoshihiro Hamada, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo: Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. PDPTA 2007: 787-793 |
| e2 | | Hideharu Amano, Andy Ye, Takeshi Ikenaga (Eds.): 2007 International Conference on Field-Programmable Technology, ICFPT 2007, Kitakyushu, Japan, December 12-14, 2007. IEEE 2007, isbn 1-4244-1472-5 |
| 2006 | ||
| j23 | | Hideharu Amano: A Survey on Dynamically Reconfigurable Processors. IEICE Transactions 89-B(12): 3179-3187 (2006) |
| j22 | | Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distrib. Syst. 17(12): 1425-1437 (2006) |
| c107 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. ISCA PDCS 2006: 24-31 |
| c106 | | Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano: Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. ARC 2006: 115-121 |
| c105 | | Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano: A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135 |
| c104 | | Hideharu Amano, Yohei Hasegawa, Shohei Abe, Kenichiro Ishikawa, Shunsuke Tsutsumi, Shunsuke Kurotaki, Takuro Nakamura, Takashi Nishimura: A Context Dependent Clock Control Mechanism for Dynamically Reconfigurable Processors. FPL 2006: 1-6 |
| c103 | | Yasunori Osana, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: Performance Evaluation of an Fpga-Based Biochemical Simulator ReCSip. FPL 2006: 1-6 |
| c102 | | Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: An FPGA Implementation of High Throughput Stochastic Simulator for Large-Scale Biochemical Systems. FPL 2006: 1-6 |
| c101 | | Shohei Abe, Yohei Hasegawa, Takao Toi, Takeshi Inuo, Hideharu Amano: An adaptive Viterbi decoder on the dynamically reconfigurable processor. FPT 2006: 285-288 |
| c100 | | Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano: Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP 2006: 479-486 |
| c99 | | Yohei Hasegawa, Shohei Abe, Shunsuke Kurotaki, Vu Manh Tuan, Naohiro Katsura, Takuro Nakamura, Takashi Nishimura, Hideharu Amano: Performance and power analysis of time-multiplexed execution on dynamically reconfigurable processor. IPDPS 2006 |
| c98 | | Masayasu Suzuki, Yohei Hasegawa, Vu Manh Tuan, Shohei Abe, Hideharu Amano: A cost-effective context memory structure for dynamically reconfigurable processors. IPDPS 2006 |
| c97 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218 |
| 2005 | ||
| j21 | | Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. IEICE Transactions 88-D(1): 109-118 (2005) |
| j20 | | Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: Path selection algorithm: the strategy for designing deterministic routing from alternative paths. Parallel Computing 31(1): 117-130 (2005) |
| j19 | | Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano: The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Computing 31(3-4): 352-370 (2005) |
| j18 | | Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano: Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. IEEE Trans. Parallel Distrib. Syst. 16(8): 747-759 (2005) |
| c96 | | Katsuaki Deguchi, Shohei Abe, Masayasu Suzuki, Kenichiro Anjo, Toru Awashima, Hideharu Amano: Implementing core tasks of JPEG2000 Encoder on the Dynamically Reconfigurable Processor. ARCS Workshops 2005: 12-18 |
| c95 | | Hideharu Amano, Shohei Abe, Yohei Hasegawa, Katsuaki Deguchi, Masayasu Suzuki: Performance and Cost Analysis of Time-Multiplexed Execution on the Dynamically Reconfigurable Processor. FCCM 2005: 315-316 |
| c94 | | Yohei Hasegawa, Shohei Abe, Katsuaki Deguchi, Masayasu Suzuki, Hideharu Amano: Time-multiplexed execution on the dynamically reconfigurable processor: a performance/cost evaluation. FPGA 2005: 265 |
| c93 | | Hideharu Amano, Shohei Abe, Katsuaki Deguchi, Yohei Hasegawa: An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? FPL 2005: 347-352 |
| c92 | | Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Masato Yoshimi, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. FPL 2005: 574-577 |
| c91 | | Naoki Iwanaga, Yuichiro Shibata, Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Tomonori Fukushima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri: Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. FPL 2005: 666-669 |
| c90 | | Vasutan Tunbunheng, Masayasu Suzuki, Hideharu Amano: RoMultiC: Fast and Simple Configuration Data Multicasting Scheme for Coarse Grain Reconfigurable Devices. FPT 2005: 129-136 |
| c89 | | Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima: An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT 2005: 163-170 |
| c88 | | Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hiroaki Kitano, Hideharu Amano: The Design of Scalable Stochastic Biochemical Simulator on FPGA. FPT 2005: 339-340 |
| c87 | | Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. ICPP 2005: 567-576 |
| c86 | | Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280 |
| c85 | | Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Yow Iwaoka, Yuichiro Shibata, Hiroaki Kitano, Akira Funahashi, Noriko Hiroi, Hideharu Amano: An FPGA-Based, Multi-model Simulation Method for Biochemical Systems. IPDPS 2005 |
| c84 | | Shunsuke Kurotaki, Noriaki Suzuki, Kazuhiro Nakadai, Hiroshi G. Okuno, Hideharu Amano: Implementation of active direction-pass filter on dynamically reconfigurable processor. IROS 2005: 3175-3180 |
| c83 | | Yasuo Miyabe, Akira Kitamura, Yoshihiro Hamada, Tomotaka Miyashiro, Tetsu Izawa, Noboru Tanabe, Hironori Nakajo, Hideharu Amano: Implementation and Evaluation of the Mechanisms for Low Latency Communication on DIMMnet-2. ISHPC 2005: 211-218 |
| c82 | | Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo: Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. PDCAT 2005: 778-780 |
| c81 | | Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano: Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123 |
| c80 | | Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo: A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. PDPTA 2005: 461-467 |
| c79 | | Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349 |
| 2004 | ||
| j17 | | Yasunori Osana, Tomonori Fukushima, Masato Yoshimi, Hideharu Amano: An FPGA-Based Acceleration Method for Metabolic Simulation. IEICE Transactions 87-D(8): 2029-2037 (2004) |
| c78 | | Masato Sumiyoshi, Takashi Midorikawa, Yasuki Tanabe, Hideharu Amano: Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. ISCA PDCS 2004: 296-301 |
| c77 | | Yasunori Osana, Tomonori Fukushima, Hideharu Amano: ReCSiP: a reconfigurable cell simulation platform: accelerating biological applications with FPGA. ASP-DAC 2004: 731-733 |
| c76 | | |
| c75 | | Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura: Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC 2004: 301-311 |
| c74 | | Noriaki Suzuki, Shunsuke Kurotaki, Masayasu Suzuki, Naoto Kaneko, Yutaka Yamada, Katsuaki Deguchi, Yohei Hasegawa, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takeo Toi, Toru Awashima: Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor. FCCM 2004: 328-329 |
| c73 | | Masato Yoshimi, Yasunori Osana, Tomonori Fukushima, Hideharu Amano: Stochastic Simulation for Biochemical Reactions on FPGA. FPL 2004: 105-114 |
| c72 | | Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki: Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. FPL 2004: 464-473 |
| c71 | | Masayasu Suzuki, Yohei Hasegawa, Yutaka Yamada, Naoto Kaneko, Katsuaki Deguchi, Hideharu Amano, Kenichiro Anjo, Masato Motomura, Kazutoshi Wakabayashi, Takao Toi, Toru Awashima: Stream applications on the dynamically reconfigurable processor. FPT 2004: 137-144 |
| c70 | | Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS 2004 |
| c69 | | Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano: A New Memory Module for Memory Intensive Applications. PARELEC 2004: 123-128 |
| 2003 | ||
| c68 | | Tomohiro Otsuka, Konosuke Watanabe, Junichiro Tsuchiya, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Hideharu Amano: Performance Evaluation of a Prototype of RHiNET-2: A Network-based Distributed Parallel Computing System. Applied Informatics 2003: 738-743 |
| c67 | | Kenta Yasufuku, Riku Ogawa, Keisuke Iwai, Hideharu Amano: MAPLE chip: a processing element for a static scheduling centric multiprocessor. ASP-DAC 2003: 575-576 |
| c66 | | Konosuke Watanabe, Tomohiro Otsuka, Junichiro Tsuchiya, Hideharu Amano, Hiroshi Harada, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh: Performance Evaluation of RHiNET-2/NI: A Network Interface for Distributed Parallel Computing Systems. CCGRID 2003: 318-325 |
| c65 | | Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano: Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. CLUSTER 2003: 395- |
| c64 | | Hideharu Amano, Akiya Jouraku, Kenichiro Anjo: A Dynamically Adaptive Switching Fabric on a Multicontext Reconfigurable Device. FPL 2003: 161-170 |
| c63 | | Toshiro Kitaoka, Hideharu Amano, Kenichiro Anjo: Reducing the Configuration Loading Time of a Coarse Grain Multicontext Reconfigurable Device. FPL 2003: 171-180 |
| c62 | | Yasunori Osana, Tomonori Fukushima, Hideharu Amano: Implementation of ReCSiP: A ReConfigurable Cell SImulation Platform. FPL 2003: 766-775 |
| c61 | | Yoshinori Adachi, Kenichiro Ishikawa, Satoshi Tsutsumi, Hideharu Amano: An implementation of the Rijndael on Async-WASMII. FPT 2003: 44-51 |
| c60 | | Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano: Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. ICPP 2003: 527- |
| c59 | | Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano: Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154 |
| c58 | | Noriaki Suzuki, Hideharu Amano: Performance Evaluation of Instruction Set Architecture of MBP-Light: A Distributed Memory Controller for a Large Scale Multiprocessor. PDPTA 2003: 1155-1164 |
| e1 | | Alexander V. Veidenbaum, Kazuki Joe, Hideharu Amano, Hideo Aiso (Eds.): High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings. Lecture Notes in Computer Science 2858, Springer 2003, isbn 3-540-20359-1 |
| 2002 | ||
| j16 | | Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. Cluster Computing 5(1): 7-17 (2002) |
| c57 | | Naoto Kaneko, Hideharu Amano: A General Hardware Design Model for Multicontext FPGAs. FPL 2002: 1037-1047 |
| c56 | | Naoyuki Izu, Tomonori Yokoyama, Junichiro Tsuchiya, Konosuke Watanabe, Hideharu Amano: RHiNET/NI: A Reconfigurable Network Interface for Cluster Computing. FPL 2002: 1118-1121 |
| c55 | | Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi: Routing Algorithms Based on 2D Turn Model for Irregular Networks. ISPAN 2002: 289-294 |
| c54 | | Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano: Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. PARELEC 2002: 9-14 |
| c53 | | Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. PDPTA 2002: 1431-1437 |
| 2001 | ||
| j15 | | Hiroaki Nishi, Koji Tasho, Tomohiro Kudoh, Hideharu Amano: A network switch for supporting high-performance parallel processing by computers distributed in local areas. Systems and Computers in Japan 32(14): 24-33 (2001) |
| j14 | | Yulu Yang, Akira Funahashi, Akiya Jouraku, Hiroaki Nishi, Hideharu Amano, Toshinori Sueyoshi: Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. IEEE Trans. Parallel Distrib. Syst. 12(7): 701-715 (2001) |
| c52 | | Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano: MMLRU Selection Function: An Output Selection Function on Adaptive Routing. ISCA PDCS 2001: 1-6 |
| c51 | | Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano: A prototype chip of multicontext FPGA with DRAM for virtual hardware. ASP-DAC 2001: 17-18 |
| c50 | | Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano: The impact of output selection function on adaptive routing. Computers and Their Applications 2001: 241-246 |
| c49 | | Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano: L-Turn Routing: An Adaptive Routing in Irregular Networks. ICPP 2001: 383-392 |
| 2000 | ||
| j13 | | Shinji Nishimura, K. Harasawa, N. Matsudaira, S. Akutsu, Tomohiro Kudoh, Hiroaki Nishi, Hideharu Amano: RHiNET-2/SW a Hight-throughput, Compact Network-switch Using 8.8-Gbit/s Optical Interconnection. New Generation Comput. 18(2): 187-197 (2000) |
| c48 | | Takahiro Kawaguchi, Takayuki Suzuki, Hideharu Amano: A floating point arithmetic unit for a static scheduling and compiler oriented multiprocessor system. ASP-DAC 2000: 31-32 |
| c47 | | Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: MEMOnet : Network interface plugged into a memory slot. CLUSTER 2000: 17-16 |
| c46 | | Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano: A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. FCCM 2000: 291-294 |
| c45 | | Yuichiro Shibata, Masaki Uno, Hideharu Amano, Koichiro Furuta, Taro Fujii, Masato Motomura: A Virtual Hardware System on a Dynamically Reconfigurable Logic Device. FCCM 2000: 295-296 |
| c44 | | Ou Yamamoto, Yuichiro Shibata, Hitoshi Kurosawa, Hideharu Amano: A Reconfigurable Stochastic Model Simulator for Analysis of Parallel Systems. FPL 2000: 475-484 |
| c43 | | Hideharu Amano, Yuichiro Shibata, Masaki Uno: Reconfigurable Systems: New Activities in Asia. FPL 2000: 585-594 |
| c42 | | Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hideharu Amano: Dataflow Partitioning and Scheduling Algorithms for WASMII, a Virtual Hardware. FPL 2000: 685-694 |
| c41 | | Hiroaki Nishi, Koji Tasho, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano: A Local Area System Network RHinet-1: A Network for High Performance Parallel Computing. HPDC 2000: 296-297 |
| c40 | | Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano: On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. ISPAN 2000: 186-194 |
| c39 | | Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano: Coherence Protocol for Home Proxy Cache on RHiNET. PDPTA 2000 |
| 1999 | ||
| j12 | | Junji Yamamoto, Takashi Fujiwara, T. Komeda, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: Performance evaluation of SNAIL: A multiprocessor based on the simple serial synchronized multistage interconnection network architecture. Parallel Computing 25(9): 1081-1103 (1999) |
| c38 | | Masaki Wakabayashi, Keisuke Inoue, Hideharu Amano: ISIS: Multiprocessor Simulator Library. Applied Informatics 1999: 198-200 |
| c37 | | Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano: A Routing Algorithm for DS-WDM Ring. Applied Informatics 1999: 562-565 |
| c36 | | Takahiro Kawaguchi, Takashi Fujiwara, Katsuto Sakamoto, Keisuke Iwai, Hideharu Amano: Floating Point Arithmetic Unit for the Custom Processor Maple. Applied Informatics 1999: 578-580 |
| c35 | | Atsushi Takayama, Yuichiro Shibata, Keisuke Iwai, Hidenori Miyazaki, Koichi Higure, Xiao-ping Ling, Hideharu Amano: Implementation and Evaluation of the Compiler for WASMII, a Virtual Hardware System. ICPP Workshops 1999: 346-351 |
| c34 | | Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano: Internal Parallelization of Data-Driven Virtual Hardware. ICPP Workshops 1999: 366- |
| c33 | | Qin Fan, Yulu Yang, Akira Funahashi, Hideharu Amano: A Torus Assignment for an Interconnection Network Recursive Diagonal Torus. ISPAN 1999: 74-79 |
| c32 | | Fumiharu Morisawa, Daisuke Kawakami, Kensuke Tanaka, Hideharu Amano: An Educational System of LSI Design with Free-Wares for VDEC. MSE 1999: 61-62 |
| 1998 | ||
| j11 | | Asami Miyajima, Kazumasa Nukata, Hideharu Amano, Yuichiro Anzai: Design and implementation of reconfigurable sensing system for networked robots. Advanced Robotics 13(3): 253-254 (1998) |
| j10 | | Ou Yamamoto, Takuya Terasawa, Hideharu Amano: An analysis of fairness and overhead in the arbitration protocol of the IEEE Futurebus standard. Systems and Computers in Japan 29(13): 66-77 (1998) |
| c31 | | Takashi Midorikawa, Takayuki Kamei, Toshihiro Hanawa, Hideharu Amano: The MINC (Multistage Interconnection Network with Cache Control Mechanism) Chip. ASP-DAC 1998: 337-338 |
| c30 | | Hideharu Amano, Yuichiro Shibata: Reconfigurable Systems: Activities in Asia and South Pacific (Embedded Tutorial). ASP-DAC 1998: 453-457 |
| c29 | | Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Ling, Hideharu Amano: HOSMII: A Virtual Hardware Integrated with DRAM. IPPS/SPDP Workshops 1998: 85-90 |
| 1997 | ||
| j9 | | Takuya Terasawa, Keisuke Inoue, Hitoshi Kurosawa, Hideharu Amano: A study on snoop cache systems for single-chip multiprocessors. Systems and Computers in Japan 28(2): 62-72 (1997) |
| c28 | | Takayuki Kamei, Masashi Sasahara, Hideharu Amano: An LSI implementation of the simple serial synchronized multistage interconnection network. ASP-DAC 1997: 673-674 |
| c27 | | Hiroaki Nishi, Hideharu Amano, Katsunobu Nishimura, Kenichiro Anjo, Tomohiro Kudoh: The RDT network router chip. ASP-DAC 1997: 675-676 |
| c26 | | Toru Kisuki, Masaki Wakabayashi, Junji Yamamoto, Keisuke Inoue, Hideharu Amano: Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors. Euro-Par 1997: 793-797 |
| c25 | | Kazumasa Nukata, Yuichiro Shibata, Hideharu Amano, Yuichiro Anzai: A reconfigurable sensor-data processing system for personal robots. FPL 1997: 491-500 |
| c24 | | Akira Funahashi, Toshihiro Hanawa, Hideharu Amano, Tomohiro Kudoh: Adaptive Routing on the Recursive Diagonal Torus. ISHPC 1997: 171-182 |
| c23 | | Xiaoshe Dong, Tomohiro Kudoh, Hideharu Amano: Wavelength Division Multiple Access Ring - Virtual Topology on a Simple Ring Network. ISPAN 1997: 30-36 |
| c22 | | Xiao-ping Ling, Yuichiro Shibata, Hidenori Miyazaki, Hideharu Amano, Koichi Higure: Total System Image of the Reconfigurable Machine WASMII. PDPTA 1997: 1092-1096 |
| 1996 | ||
| j8 | | Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi: Recursive Diagonal Torus (RDT): An Interconnection Network for the Massively Parallel Computers. Systems and Computers in Japan 27(9): 43-54 (1996) |
| c21 | | Yuichiro Shibata, Xiao-ping Ling, Hideharu Amano: An Emulation System of the WASMII: A Data Driven Computer on a Virtual Hardware. FPL 1996: 55-64 |
| c20 | | Keisuke Inoue, Toru Kisuki, Michitaka Okuno, Etsuko Shimizu, Takuya Terasawa, Hideharu Amano: ATTEMPT-1: A Reconfigurable Multiprocessor Testbed. FPL 1996: 200-209 |
| 1995 | ||
| j7 | | Kyotaro Suzuki, Hideharu Amano, Yoshiyasu Takefuji: Neural network parallel computing for multi-layer channel routing problems. Neurocomputing 8(2): 141-156 (1995) |
| j6 | | Takuya Terasawa, Ou Yamamoto, Tomohiro Kudoh, Hideharu Amano: A Performance Evaluation of the Multiprocessor Testbed ATTEMPT-0. Parallel Computing 21(5): 701-730 (1995) |
| j5 | | Kalidou Gaye, Toshihiro Hanawa, Hideharu Amano: An analysis of the hot spot contention and message combining on the simple serial synchronized-multistage interconnection network. Systems and Computers in Japan 26(9): 1-12 (1995) |
| j4 | | Xiao-ping Ling, Hideharu Amano: WASMII: An MPLD with data-driven control on a virtual hardware. The Journal of Supercomputing 9(3): 253-276 (1995) |
| c19 | | Tomohiro Kudoh, Hideharu Amano, Takashi Matsumoto, Kei Hiraki, Yulu Yang, Katsunobu Nishimura, Koichi Yoshimura, Yasuhito Fukushima: Hierarchical Bit-Map Directory Schemes on the RDT Interconnection Network for a Massively Parallel Processor JUMP-1. ICPP (1) 1995: 186-193 |
| c18 | | Junji Yamamoto, D. Hattori, Jun-ichi Yamato, T. Tokuyoshi, Y. Yamaguchi, Hideharu Amano: A Preprocessing System of the EULASH: An Environment for Efficient use of Multiprocessors with Local Memory. Parallel and Distributed Computing and Systems 1995: 68-71 |
| 1994 | ||
| c17 | | Xiao-yu Chen, Xiao-ping Ling, Hideharu Amano: Software Environment for WASMII: a Data Driven Machine with a Virtual Hardware. FPL 1994: 208-219 |
| c16 | | Toshihiro Hanawa, Hideharu Amano, Yoshifumi Fujikawa: Multistage Interconnection Networks with Multiple Outlets. ICPP (1) 1994: 1-8 |
| c15 | | Masashi Sasahara, Jun Terada, Luo Zhou, Kalidou Gaye, Jun-ichi Yamato, Satoshi Ogura, Hideharu Amano: SNAIL: A Multiprocessor Based on the Simple Serial Synchronized Multistage Interconnection Network Architecture. ICPP (1) 1994: 117-120 |
| 1993 | ||
| j3 | | Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa: A query-based parallel logic simulation algorithm. Systems and Computers in Japan 24(2): 11-21 (1993) |
| c14 | | Xiao-ping Ling, Hideharu Amano: Performance evaluation of WASMII: a data driven computer on a virtual hardware. PARLE 1993: 610-621 |
| c13 | | Yulu Yang, Hideharu Amano, Hidetomo Shibamura, Toshinori Sueyoshi: Recursive Diagonal Torus: An Interconnection Network for Massively Parallel Computers. SPDP 1993: 591-595 |
| 1992 | ||
| c12 | | Tomohiro Kudoh, Tetsuro Kimura, Hideharu Amano, Takuya Terasawa: A Parallel Logic Simulation Algorithm Based on Query. ICPP (3) 1992: 262-266 |
| c11 | | Hideharu Amano, Luo Zhou, Kalidou Gaye: SSS (Simple Serial Synchronized)-MIN: A Novel Multi Stage Interconnection Architecture for Multiprocessors. IFIP Congress (1) 1992: 571-577 |
| 1991 | ||
| j2 | | Taisuke Boku, Tomohiro Kudoh, Hideharu Amano, Tetsuro Kimura: NCC: A concurrent description language for scientific calculation on multiprocessors. Systems and Computers in Japan 22(12): 1-10 (1991) |
| c10 | | |
| 1990 | ||
| j1 | | Hideharu Amano, Taisuke Boku, Tomohiro Kudoh: (SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations. IEEE Trans. Computers 39(7): 889-905 (1990) |
| c9 | | |
| 1989 | ||
| c8 | | Hideharu Amano, Takuya Terasawa, Tomohiro Kudoh: Cache with Synchronization Mechanism. IFIP Congress 1989: 1001-1006 |
| c7 | | Jun Miyazaki, Kenji Takeda, Hideharu Amano, Hideo Aiso: A New Version of a Parallel Production System Machine, MANJI-II. IWDM 1989: 317-330 |
| c6 | | Xiao-ping Ling, Hideharu Amano: A static scheduling system for a parallel machine (SM)2-II. PARLE (1) 1989: 118-135 |
| 1988 | ||
| c5 | | Taisuke Boku, Shigehiro Nomura, Hideharu Amano: IMPULSE: A High Performance Processing Unit for Multiprocessors for Scientific Calculation. ISCA 1988: 365-372 |
| 1987 | ||
| c4 | | Jun Miyazaki, Hideharu Amano, Kenji Takeda, Hideo Aiso: A Shared Memory Architecture for MANJI Production System Machine. IWDM 1987: 517-531 |
| 1986 | ||
| c3 | | Chizuko Saito, Hideharu Amano, Tomohiro Kudoh, Hideo Aiso: An Adaptable Cluster Structure of (SM)²-II. CONPAR 1986: 53-60 |
| 1985 | ||
| c2 | | Hideharu Amano, Taisuke Boku, Tomohiro Kudoh, Hideo Aiso: (SM)²-II: A New Version of the Sparse Matrix Solving Machine. ISCA 1985: 100-107 |
| 1983 | ||
| c1 | | Hideharu Amano, Takaichi Yoshida, Hideo Aiso: (SM)2: Sparse Matrix Solving Machine. ISCA 1983: 213-220 |
Colors in the list of coauthors
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