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 | 2012 | |
|---|---|---|
| j2 |      | Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Koji Nii, Masahiko Yoshimoto, Hiroshi Kawaguchi: Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Transactions 95-A(8): 1359-1365 (2012) |
| j1 | | Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Transactions 95-C(10): 1675-1681 (2012) |
| c2 | | Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Shintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto: Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 |
| 2011 | ||
| c1 | | Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura, Hiroshi Kawaguchi, Masahiko Yoshimoto: Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 |
| 1 | Shintaro Izumi | |
| 2 | Hiroshi Kawaguchi | |
| 3 | D. Kozuwa | |
| 4 | Yusuke Matsunaga | |
| 5 | Koji Nii | |
| 6 | Shunsuke Okumura | |
| 7 | Taiga Takata | |
| 8 | Hiroto Yasuura | |
| 9 | Masahiko Yoshimoto | |
| 10 | Shusuke Yoshimoto | |
| 11 | Masayoshi Yoshimura |
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