Bharadwaj Amrutur
List of publications from the DBLP Bibliography Server - FAQ
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 | 2013 | |
|---|---|---|
| j14 |      | Basavaraj Talwar, Bharadwaj Amrutur: Traffic engineered NoC for streaming applications. Microprocessors and Microsystems - Embedded Hardware Design 37(3): 333-344 (2013) |
| c34 | | Rajath Vasudevamurthy, Bharadwaj Amrutur: Multiphase Technique to Speed-up Delay Measurement via Sub-sampling. VLSI Design 2013: 185-190 |
| 2012 | ||
| j13 | | Pramod Murali, Ranjit K., Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy: A CMOS Gas Sensor Array Platform With Fourier Transform Based Impedance Spectroscopy. IEEE Trans. on Circuits and Systems 59-I(11): 2507-2517 (2012) |
| j12 | | Pratap Kumar Das, Bharadwaj Amrutur: An Accurate Fractional Period Delay Generation System. IEEE T. Instrumentation and Measurement 61(7): 1924-1932 (2012) |
| j11 | | Nandish Ashutosh Mehta, Bharadwaj Amrutur: Dynamic Supply and Threshold Voltage Scaling for CMOS Digital Circuits Using In-Situ Power Monitor. IEEE Trans. VLSI Syst. 20(5): 892-901 (2012) |
| c33 | | Aparna Mandke Dani, Y. N. Srikant, Bharadwaj Amrutur: Efficient cache exploration method for a tiled chip multiprocessor. HiPC 2012: 1-6 |
| c32 | | Aparna Mandke Dani, Bharadwaj Amrutur, Y. N. Srikant, Chiranjib Bhattacharyya: TCP: Thread Contention Predictor for Parallel Programs. PDP 2012: 19-26 |
| c31 | | Manodipan Sahoo, Bharadwaj Amrutur: Comparison of OpAmp Based and Comparator Based Switched Capacitor Filter. VDAT 2012: 180-189 |
| c30 | | Pramod Murali, Navakanta Bhat, Gaurab Banerjee, Bharadwaj Amrutur, K. N. Bhat, Praveen C. Ramamurthy: CMOS Gas Sensor Array Platform with Fourier Transform Based Impedance Spectroscopy. VLSI Design 2012: 173-178 |
| 2011 | ||
| j10 | | Vikram Chaturvedi, Bharadwaj Amrutur: An Area-Efficient Noise-Adaptive Neural Amplifier in 130 nm CMOS Technology. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(4): 536-545 (2011) |
| j9 | | Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi: Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding. IEEE Trans. Circuits Syst. Video Techn. 21(2): 225-230 (2011) |
| j8 | | Rakesh Gnana David Jeyasingh, Navakanta Bhat, Bharadwaj S. Amrutur: Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique. IEEE Trans. VLSI Syst. 19(2): 295-304 (2011) |
| j7 | | Bharadwaj Amrutur, Pratap Kumar Das, Rajath Vasudevamurthy: 0.84 ps Resolution Clock Skew Measurement via Subsampling. IEEE Trans. VLSI Syst. 19(12): 2267-2275 (2011) |
| c29 | | Pushkar Gorur, Bharadwaj Amrutur: Speeded up Gaussian Mixture Model algorithm for background subtraction. AVSS 2011: 386-391 |
| c28 |  | Siva Rama Krishna V., Bharadwaj Amrutur, Navakanta Bhat, Chakra Pani K., Sampath Srinivasan: Detection of Glycated Hemoglobin using 3-Aminophenylboronic Acid Modified Graphene Oxide. BIODEVICES 2011: 109-113 |
| c27 | | Rajath Vasudevamurthy, Pratap Kumar Das, Bharadwaj Amrutur: A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test. ISCAS 2011: 2035-2038 |
| c26 | | Kaushik Ghosal, S. A. Kannan, Bharadwaj Amrutur: A power scalable receiver front-end at 2.4 GHz. ISCAS 2011: 2765-2768 |
| c25 | | Aparna Mandke Dani, Bharadwaj Amrutur, Y. N. Srikant: Applying genetic algorithms to optimize the power in tiled SNUCA chip multicore architectures. SAC 2011: 1090-1091 |
| c24 | | Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat: Power Scalable Digital Baseband Architecture for IEEE 802.15.4. VLSI Design 2011: 30-35 |
| c23 | | Vikram Chaturvedi, Bharadwaj Amrutur: A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology. VLSI Design 2011: 328-333 |
| 2010 | ||
| j6 | | M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji: False Error Vulnerability Study of On-line Soft Error Detection Mechanisms. J. Electronic Testing 26(3): 323-335 (2010) |
| j5 | | Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. on CAD of Integrated Circuits and Systems 29(7): 1056-1069 (2010) |
| c22 | | Nandish Ashutosh Mehta, Gururaj V. Naik, Bharadwaj S. Amrutur: In-situ power monitoring scheme and its application in dynamic voltage and threshold scaling for digital CMOS integrated circuits. ISLPED 2010: 259-264 |
| c21 | | Aparna Mandke Dani, Keshavan Varadarajan, Bharadwaj Amrutur, Y. N. Srikant: Accelerating multi-core simulators. SAC 2010: 2377-2382 |
| 2009 | ||
| j4 | | Ajit Gupte, Bharadwaj Amrutur: Adaptive Global Elimination Algorithm for Low Power Motion Estimation. J. Low Power Electronics 5(1): 1-16 (2009) |
| j3 | | K. Sreejith, Bharadwaj Amrutur, Ashok Balivada: A Workload Based Lookup Table for Minimal Power Operation Under Supply and Body Bias Control. J. Low Power Electronics 5(2): 173-184 (2009) |
| j2 | | Ajit Gupte, Bharadwaj Amrutur: Adaptive Global Elimination Algorithm for Low Power Motion Estimation (J. Low Power Electronics 5: 1-16 (2009)). J. Low Power Electronics 5(2): 255-256 (2009) |
| c20 | | Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur: Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. VLSI Design 2009: 163-168 |
| 2008 | ||
| j1 | | Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan: Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electronics 4(3): 301-319 (2008) |
| c19 | | Ajit Gupte, Bharadwaj Amrutur: An adaptive, feature-based low power motion estimation algorithm. ICME 2008: 1013-1016 |
| c18 | | M. Kiran Kumar Reddy, Bharadwaj S. Amrutur, Rubin A. Parekhji: False Error Study of On-line Soft Error Detection Mechanisms. IOLTS 2008: 53-58 |
| c17 | | Jagdish Nayayan Pandey, Bharadwaj Amrutur, Sudhir S. Kudva: Quadrature generation techniques for frequency multiplication based oscillators. ISCAS 2008: 440-443 |
| c16 | | Arvind Madan, Bharadwaj Amrutur: Power reduction in on-chip interconnection network by serialization. ISLPED 2008: 201-204 |
| c15 | | Kannan Aryaperumal Sankaragomathi, Manodipan Sahoo, Satyam Dwivedi, Bharadwaj S. Amrutur, Navakanta Bhat: Optimal power and noise allocation for analog and digital sections of a low power radio receiver. ISLPED 2008: 271-276 |
| c14 | | Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur: Energy Reduction in SRAM using Dynamic Voltage and Frequency Management. VLSI Design 2008: 503-508 |
| c13 | | S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur: Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block. VLSI Design 2008: 509-514 |
| c12 | | Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur: A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read. VLSI Design 2008: 560-565 |
| c11 | | Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur: Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization. VLSI Design 2008: 667-672 |
| c10 | | Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind: Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations. VLSI Design 2008: 685-691 |
| 2007 | ||
| c9 | | Kaushik Rajan, Ramaswamy Govindarajan, Bharadwaj Amrutur: Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses. PACT 2007: 422 |
| c8 | | Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. N. Srikant: INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations. CASES 2007: 238-247 |
| c7 | | R. G. Raghavendra, Bharadwaj Amrutur: Area efficient loop filter design for charge pump phase locked loop. ACM Great Lakes Symposium on VLSI 2007: 148-151 |
| c6 | | Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur: A Low Power Frequency Multiplication Technique for ZigBee Transciever. VLSI Design 2007: 150-155 |
| c5 | | K. R. Viveka, Abhilasha Kawle, Bharadwaj Amrutur: Low Power Pipelined TCAM Employing Mismatch Dependent Power Allocation Technique. VLSI Design 2007: 638-646 |
| c4 | | Satish Yada, Bharadwaj S. Amrutur, Rubin A. Parekhji: Modified Stability Checking for On-line Error Detection. VLSI Design 2007: 787-792 |
| c3 | | U. K. Vijay, Bharadwaj Amrutur: Continuous Time Sigma Delta Modulator Employing a Novel Comparator Architecture. VLSI Design 2007: 919-924 |
| 2006 | ||
| c2 | | Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan: A scalable low power issue queue for large instruction window processors. ICS 2006: 167-176 |
| c1 | | Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Bharadwaj Amrutur, Ravi R. Iyer, Srihari Makineni, Donald Newell: Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. MICRO 2006: 433-442 |
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