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 | 2013 | |
|---|---|---|
| j8 |      | Bill Teng, Jason Helge Anderson: Latch-Based Performance Optimization for Field-Programmable Gate Arrays. IEEE Trans. on CAD of Integrated Circuits and Systems 32(5): 667-680 (2013) |
| c35 | | Marcel Gort, Jason Helge Anderson: Range and bitmask analysis for hardware optimization in high-level synthesis. ASP-DAC 2013: 773-779 |
| c34 | | Andrew Canis, Jason Helge Anderson, Stephen Dean Brown: Multi-pumping for resource reduction in FPGA high-level synthesis. DATE 2013: 194-197 |
| c33 | | Jason Helge Anderson, Stephen Dean Brown, Andrew Canis, Jongsok Choi: High-level synthesis with LegUp: a crash course for users and researchers. FPGA 2013: 7-8 |
| 2012 | ||
| j7 | | Marcel Gort, Jason Helge Anderson: Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010. IEEE Trans. on CAD of Integrated Circuits and Systems 31(1): 61-74 (2012) |
| j6 | | Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings: FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 31(9): 1305-1318 (2012) |
| j5 | | Jason Helge Anderson, Qiang Wang, Chirag Ravishankar: Raising FPGA Logic Density Through Synthesis-Inspired Architecture. IEEE Trans. VLSI Syst. 20(3): 537-550 (2012) |
| c32 | | Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski: Impact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems. FCCM 2012: 17-24 |
| c31 | | Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson: The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86 |
| c30 | | Warren Wai-Kit Shum, Jason Helge Anderson: Analyzing and predicting the impact of CAD algorithm noise on FPGA speed performance and power. FPGA 2012: 107-110 |
| c29 | | Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Dean Brown, Tomasz S. Czajkowski: Impact of FPGA architecture on resource sharing in high-level synthesis. FPGA 2012: 111-114 |
| c28 | | |
| c27 | | Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson: FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC 2012: 271-274 |
| 2011 | ||
| c26 | | Mark Aldham, Jason Helge Anderson, Stephen Dean Brown, Andrew Canis: Low-cost hardware profiling of run-time and energy in FPGA embedded processors. ASAP 2011: 61-68 |
| c25 | | Jason Helge Anderson, Qiang Wang: Area-efficient FPGA logic elements: Architecture and synthesis. ASP-DAC 2011: 369-375 |
| c24 | | Alireza Rakhshanfar, Jason Helge Anderson: An integer programming placement approach to FPGA clock power reduction. ASP-DAC 2011: 831-836 |
| c23 | | Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Dean Brown, Tomasz S. Czajkowski: LegUp: high-level synthesis for FPGA-based processor/accelerator systems. FPGA 2011: 33-36 |
| c22 | | Jason Luu, Jason Helge Anderson, Jonathan Rose: Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA 2011: 227-236 |
| c21 | | |
| c20 | | Marcel Gort, Jason Helge Anderson: Reducing FPGA Router Run-Time through Algorithm and Architecture. FPL 2011: 336-342 |
| c19 | | Warren Wai-Kit Shum, Jason Helge Anderson: FPGA glitch power analysis and reduction. ISLPED 2011: 27-32 |
| 2010 | ||
| c18 | | |
| c17 | | Jason Helge Anderson, Chirag Ravishankar: FPGA power reduction by guarded evaluation. FPGA 2010: 157-166 |
| c16 | | Steven Birk, J. Gregory Steffan, Jason Helge Anderson: Parallelizing FPGA placement using Transactional Memory. FPT 2010: 61-69 |
| c15 | | Marcel Gort, Jason Helge Anderson: Deterministic multi-core parallel routing for FPGAs. FPT 2010: 78-86 |
| 2009 | ||
| j4 | | Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson: Packing Techniques for Virtex-5 FPGAs. TRETS 2(3) (2009) |
| j3 | | Jason Helge Anderson, Farid N. Najm: Low-Power Programmable FPGA Routing Circuitry. IEEE Trans. VLSI Syst. 17(8): 1048-1060 (2009) |
| c14 | | Jason Helge Anderson: Emerging application domains: research challenges and opportunities for FPGAs. FPGA 2009: 1-2 |
| c13 | | Qiang Wang, Subodh Gupta, Jason Helge Anderson: Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22 |
| c12 | | Jason Helge Anderson, Qiang Wang: Improving logic density through synthesis-inspired architecture. FPL 2009: 105-111 |
| c11 | | Safeen Huda, Muntasir Mallick, Jason Helge Anderson: Clock gating architectures for FPGA power reduction. FPL 2009: 112-118 |
| 2008 | ||
| c10 | | Taneem Ahmed, Paul D. Kundarewich, Jason Helge Anderson, Brad L. Taylor, Rajat Aggarwal: Architecture-specific packing for virtex-5 FPGAs. FPGA 2008: 5-13 |
| 2006 | ||
| j2 | | Jason Helge Anderson, Farid N. Najm: Active leakage power optimization for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 423-437 (2006) |
| 2004 | ||
| j1 | | Jason Helge Anderson, Farid N. Najm: Power estimation techniques for FPGAs. IEEE Trans. VLSI Syst. 12(10): 1015-1027 (2004) |
| c9 | | Jason Helge Anderson, Farid N. Najm: Interconnect capacitance estimation for FPGAs. ASP-DAC 2004: 713-718 |
| c8 | | Jason Helge Anderson, Farid N. Najm, Tim Tuan: Active leakage power optimization for FPGAs. FPGA 2004: 33-41 |
| c7 | | Jason Helge Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng: Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. FPL 2004: 168-178 |
| c6 | | Jason Helge Anderson, Farid N. Najm: Low-power programmable routing circuitry for FPGAs. ICCAD 2004: 602-609 |
| 2003 | ||
| c5 | | Jason Helge Anderson, Farid N. Najm: Switching activity analysis and pre-layout activity prediction for FPGAs. SLIP 2003: 15-21 |
| 2002 | ||
| c4 | | Jason Helge Anderson, Farid N. Najm: Power-aware technology mapping for LUT-based FPGAs. FPT 2002: 211-218 |
| 2000 | ||
| c3 | | Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman: A Placement Algorithm for FPGA Designs with Multiple I/O Standards. FPL 2000: 211-220 |
| 1998 | ||
| c2 | | Jason Helge Anderson, Stephen Dean Brown: Technology Mapping for Large Complex PLDs. DAC 1998: 698-703 |
| c1 | | Jason Helge Anderson, Stephen Dean Brown: An LPGA with Foldable PLA-style Logic Blocks. FPGA 1998: 244-252 |
Colors in the list of coauthors
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