Federico Angiolini

Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad: Computing Accurate Performance Bounds for Best Effort Networks-on-Chip. IEEE Trans. Computers 62(3): 452-467 (2013)

Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal: Design Issues and Considerations for Low-Cost 3-D TSV IC Technology. J. Solid-State Circuits 46(1): 293-307 (2011)

Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini: Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip. IEEE Trans. on CAD of Integrated Circuits and Systems 30(1): 124-134 (2011)

Jaume Joven, Andrea Marongiu, Federico Angiolini, Luca Benini, Giovanni De Micheli: Exploring programming model-driven QoS support for NoC-based platforms. CODES+ISSS 2010: 65-74

Giovanni De Micheli, Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Federico Angiolini, Antonio Pullini: Networks on Chips: from research to products. DAC 2010: 300-305

Dragomir Milojevic, Trevor Carlson, Kris Croes, Riko Radojcic, Diana F. Ragett, Dirk Seynhaeve, Federico Angiolini, Geert Van der Plas, Paul Marchal: Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. 3DIC 2009: 1-6

Igor Loi, Federico Angiolini, Luca Benini: Synthesis of low-overhead configurable source routing tables for network interfaces. DATE 2009: 262-267

Dara Rahmati, Srinivasan Murali, Luca Benini, Federico Angiolini, Giovanni De Micheli, Hamid Sarbazi-Azad: A method for calculating hard QoS guarantees for Networks-on-Chip. ICCAD 2009: 579-586

Mohammad Reza Kakoee, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Ciprian Seiculescu, Luca Benini: A floorplan-aware interactive tool flow for NoC design and synthesis. SoCC 2009: 379-382

Suresh Srinivasan, Lin Li, Martino Ruggiero, Federico Angiolini, Narayanan Vijaykrishnan, Luca Benini: Exploring architectural solutions for energy optimisations in bus-based system-on-chip. IET Computers & Digital Techniques 2(5): 347-354 (2008)

David Atienza, Federico Angiolini, Srinivasan Murali, Antonio Pullini, Luca Benini, Giovanni De Micheli: Network-on-Chip design and synthesis outlook. Integration 41(3): 340-359 (2008)

Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen: A Reactive and Cycle-True IP Emulator for MPSoC Exploration. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 109-122 (2008)

Igor Loi, Federico Angiolini, Luca Benini: Developing Mesochronous Synchronizers to Enable 3D NoCs. DATE 2008: 1414-1419

Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini: Bringing NoCs to 65 nm. IEEE Micro 27(5): 75-85 (2007)

Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini: A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. IEEE Trans. on CAD of Integrated Circuits and Systems 26(3): 421-434 (2007)

Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli: Timing-Error-Tolerant Network-on-Chip Design Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 26(7): 1297-1310 (2007)

Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini: Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI Design 2007 (2007)

Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli: Interactive presentation: Improving the fault tolerance of nanometric PLA designs. DATE 2007: 570-575

Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini: NoC Design and Implementation in 65nm Technology. NOCS 2007: 273-282

Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo: Contrasting a NoC and a traditional interconnect fabric with layout awareness. DATE 2006: 124-129

Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini: An integrated open framework for heterogeneous MPSoC design space exploration. DATE 2006: 1145-1150

Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Designing application-specific networks on chips with floorplan information. ICCAD 2006: 355-362

Federico Angiolini, David Atienza, Srinivasan Murali, Luca Benini, Giovanni De Micheli: Reliability Support for On-Chip Memories Using Networks-on-Chip. ICCD 2006

Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo: Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips. VLSI-SoC 2006: 158-163

Federico Angiolini, Luca Benini, Alberto Caprara: An efficient profile-based algorithm for scratchpad memory partitioning. IEEE Trans. on CAD of Integrated Circuits and Systems 24(11): 1660-1676 (2005)

Shankar Mahadevan, Federico Angiolini, Michael Storgaard, Rasmus Grøndahl Olsen, Jens Sparsø, Jan Madsen: A Network Traffic Generator Model for Fast Network-on-Chip Simulation. DATE 2005: 780-785

Stergios Stergiou, Federico Angiolini, Salvatore Carta, Luigi Raffo, Davide Bertozzi, Giovanni De Micheli: ast pipes Lite: A Synthesis Oriented Design Library For Networks on Chips. DATE 2005: 1188-1193

Federico Angiolini, Paolo Meloni, Luca Benini, Salvatore Carta, Luigi Raffo: Networks on Chips: A Synthesis Perspective. PARCO 2005: 745-752

Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini: Fault tolerance overhead in network-on-chip flow control schemes. SBCCI 2005: 224-229

Suresh Srinivasan, Federico Angiolini, Martino Ruggiero, Luca Benini, Narayanan Vijaykrishnan: Simultaneous memory and bus partitioning for SoC architectures. SoCC 2005: 125-128

Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen: A Traffic Injection Methodology with Support for System-Level Synchronization. VLSI-SoC 2005: 145-161

Federico Angiolini, Francesco Menichelli, Alberto Ferrero, Luca Benini, Mauro Olivieri: A post-compiler approach to scratchpad mapping of code. CASES 2004: 259-267

Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon: Analyzing On-Chip Communication in a MPSoC Environment. DATE 2004: 752-757

Federico Angiolini, Luca Benini, Alberto Caprara: Polynomial-time algorithm for on-chip scratchpad memory partitioning. CASES 2003: 318-326