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Walter Anheier
2010 – today
- 2010
[p2]Ajoy Kumar Palit, Walter Anheier: Efficient Training Algorithm for Neuro-Fuzzy Network and its Application to Nonlinear Sensor Characteristic Linearization. Intelligent Systems for Automated Learning and Adaptation 2010: 72-90- [c19]Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier: Fault diagnosis of crosstalk induced glitches and delay faults. DDECS 2010: 358-363
- [c18]Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier: Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. VLSI Design 2010: 345-350
2000 – 2009
- 2009
- [c17]Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler: Timing Arc based logic analysis for false noise reduction. ICCAD 2009: 225-230
- [p1]Ajoy Kumar Palit, Walter Anheier, Dobrivoje Popovic: Electrical Load Forecasting Using a Neural-Fuzzy Approach. Natural Intelligence for Scheduling, Planning and Packing Problems 2009: 145-173
- 2008
- [j4]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: Crosstalk fault modeling in defective pair of interconnects. Integration 41(1): 27-37 (2008)
- [c16]Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler: Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED 2008: 508-513
- 2007
- [c15]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. DDECS 2007: 161-164
- 2006
- [c14]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. DFT 2006: 336-344
- [c13]Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier: Reduction of Crosstalk Pessimism using Tendency Graph Approach. ICCD 2006
- [c12]Sascha Kneip, Walter Anheier: Vergleich und Optimierung von Algorithmen zur Modulo-Multiplikation auf Smartcards. MBMV 2006: 292-301
- [c11]Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier: Modeling of Crosstalk Fault in Defective Interconnects. PATMOS 2006: 340-349
- 2005
- [c10]Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel: A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium 2005: 22-27
- [c9]Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel: ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design 2005: 354-359
- 2004
- [c8]Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel: Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT 2004: 174-182
- 2000
- [j3]A. Schubert, Walter Anheier: On Random Pattern Testability of Cryptographic VLSI Cores. J. Electronic Testing 16(3): 185-192 (2000)
1990 – 1999
- 1999
- [j2]Frank Poehl, Walter Anheier: Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. J. Electronic Testing 14(1-2): 49-55 (1999)
- [c7]H. Henkelmann, C. Bruennlein, Walter Anheier: Effiziente Methoden zum Zahlenvergleich und zur Vorzeichenerkennung in Restklassensystemen. MBMV 1999: 121-130
- 1998
- [c6]Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar: A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. VLSI Design 1998: 122-127
- 1997
- [c5]Ansgar Drolshagen, H. Henkelmann, Walter Anheier: Processor Elements for the Standard Cell Implementation of Residue Number Systems. ASAP 1997: 116-123
- 1995
- [c4]Stefan Radtke, Jens Bargfrede, Walter Anheier: Distributed automatic test pattern generation with a parallel FAN algorithm. ICCD 1995: 698-
- 1994
- [j1]N. Ebi, Bernd Lauterbach, Walter Anheier: An image analysis system for automatic data acquisition from colored scanned maps. Mach. Vis. Appl. 7(3): 148-164 (1994)
- [c3]Beom-Ik Cheon, Walter Anheier, Rainer Laur: A New Strategy for Test Pattern Generation in Sequential Circuits. ISCAS 1994: 77-80
- [c2]Bernd Lauterbach, Walter Anheier: Segmentation of Scanned Maps in Uniform Color Spaces. MVA 1994: 222-225
- 1993
- [c1]B. Lauerbach, Walter Anheier: Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen. DAGM-Symposium 1993: 733-740
Coauthor Index
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last updated on 2012-12-02 21:56 CET by the dblp team