Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Tetsuya Asai
2010 – today
- 2013
[c21]Eric Shun Fukuda, Hideyuki Kawashima, Hiroaki Inoue, Taro Fujii, Koichiro Furuta, Tetsuya Asai, Masato Motomura: C-Based Adaptive Stream Processing on Dynamically Reconfigurable Hardware: A Case Study on Window Join. ARC 2013: 220- 2012
- [c20]Kazuki Nakada, Keiji Miura, Tetsuya Asai, Hisa-aki Tanaka: Dynamical systems design of nonlinear oscillators using phase reduction approach. APCCAS 2012: 308-311
- 2011
- [j32]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya: Neuro-morphic Circuit Architectures Employing Temporal Noises and Device Fluctuations to Improve Signal-to-noise Ratio in a Single-electron Pulse-density Modulator. IJUC 7(1-2): 53-63 (2011)
- 2010
- [j31]Shin'ichi Asai, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya: High-Resistance Resistor Consisting of a Subthreshold CMOS Differential Pair. IEICE Transactions 93-C(6): 741-746 (2010)
- [j30]Yusuke Tsugita, Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: An On-Chip PVT Compensation Technique with Current Monitoring Circuit for Low-Voltage CMOS Digital LSIs. IEICE Transactions 93-C(6): 835-841 (2010)
- [j29]Takaaki Hirai, Tetsuya Asai, Yoshihito Amemiya: A CMOS Phase-Shift oscillator Based on the conduction of Heat. Journal of Circuits, Systems, and Computers 19(4): 763-772 (2010)
- [j28]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A 1-muhboxW 600- hboxppm/circhboxC Current Reference Circuit Consisting of Subthreshold CMOS Circuits. IEEE Trans. on Circuits and Systems 57-II(9): 681-685 (2010)
- [c19]Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya: Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. ICONIP (1) 2010: 188-195
2000 – 2009
- 2009
- [j27]Taichi Ogawa, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Threshold-Logic Devices Consisting of Subthreshold CMOS Circuits. IEICE Transactions 92-A(2): 436-442 (2009)
- [j26]Akira Utagawa, Tohru Sahashi, Tetsuya Asai, Yoshihito Amemiya: Stochastic Resonance in an Array of Locally-Coupled McCulloch-Pitts Neurons with Population Heterogeneity. IEICE Transactions 92-A(10): 2508-2513 (2009)
- [j25]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Low-Voltage Process-Compensated VCO with On-Chip Process Monitoring and Body-Biasing Circuit Techniques. IEICE Transactions 92-A(12): 3079-3081 (2009)
- [j24]Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici: A Neuromorphic Single-Electron Circuit for Noise-Shaping Pulse-Density Modulation. IJNMC 1(2): 80-92 (2009)
- [j23]Yuzuru Ohba, Masaki Sazawa, Kiyoshi Ohishi, Tetsuya Asai, Katsuyuki Majima, Yukio Yoshizawa, Koichi Kageyama: Sensorless Force Control for Injection Molding Machine Using Reaction Torque Observer Considering Torsion Phenomenon. IEEE Transactions on Industrial Electronics 56(8): 2955-2960 (2009)
- [c18]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. ASP-DAC 2009: 95-96
- [c17]Tomoki Iida, Tetsuya Asai, Eiichi Sano, Yoshihito Amemiya: Offset cancellation with subthreshold-operated feedback circuit for fully differential amplifiers. ICECS 2009: 140-143
- [c16]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya: Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. ICONIP (2) 2009: 384-391
- [c15]Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya: A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. IJCNN 2009: 1600-1605
- [c14]Ken Ueno, Tetsuya Asai, Yoshihito Amemiya: Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. ISCAS 2009: 5-8
- [c13]Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose: On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. ISCAS 2009: 1565-1568
- [c12]Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya: Pulse-Density Modulation with an Ensemble of Single-Electron Circuits Employing Neuronal Heterogeneity to Achieve High Temporal Resolution. NanoNet 2009: 51-56
- [r1]Tetsuya Asai: Unconventional Computing, Novel Hardware for. Encyclopedia of Complexity and Systems Science 2009: 9706-9726
- 2008
- [j22]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Noise-Induced Synchronization among Sub-RF CMOS Analog Oscillators for Skew-Free Clock Distribution. IEICE Transactions 91-A(9): 2475-2481 (2008)
- [j21]Kazuhito Yamada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: On Digital LSI Circuits Exploiting Collision-Based Fusion Gates. IJUC 4(1): 45-59 (2008)
- [c11]Kazuki Nakada, Jun Igarashi, Tetsuya Asai, Katsumi Tateno, Hatsuo Hayashi, Yoshitaka Ohtubo, Tsutomu Miki, Kiyonori Yoshii: Stochastic Synchronization and Array-Enhanced Coherence Resonance in a Bio-inspired Chemical Sensor Array. CSE 2008: 307-312
- [c10]Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya: Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. ICONIP (2) 2008: 851-858
- 2007
- [j20]Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits. IEICE Transactions 90-A(10): 2108-2115 (2007)
- [j19]Motoyoshi Takahashi, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: A CMOS Reaction-diffusion Device Using Minority-Carrier Diffusion in Semiconductors. I. J. Bifurcation and Chaos 17(5): 1713-1719 (2007)
- [j18]Andrew Kilinga Kikombo, Takahide Oya, Tetsuya Asai, Yoshihito Amemiya: Discrete Dynamical Systems Consisting of Single-electron Circuits. I. J. Bifurcation and Chaos 17(10): 3613-3617 (2007)
- [j17]Takahide Oya, Ikuko N. Motoike, Tetsuya Asai: Single-electron Circuits Performing Dendritic Pattern Formation with Nature-Inspired Cellular Automata. I. J. Bifurcation and Chaos 17(10): 3651-3655 (2007)
- [j16]Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya: A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. Neurocomputing 71(1-3): 3-12 (2007)
- [j15]
- [c9]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. ICONIP (2) 2007: 117-126
- [c8]Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. IJCNN 2007: 897-901
- [c7]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. ISCAS 2007: 3748-3751
- 2006
- [j14]Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya: A CMOS Watchdog Sensor for Certifying the Quality of Various Perishables with a Wider Activation Energy. IEICE Transactions 89-A(4): 902-907 (2006)
- [j13]Tetsuya Asai, Taishi Kamiya, Tetsuya Hirose, Yoshihito Amemiya: A subthreshold Analog MOS Circuit for Lotka-volterra Chaotic oscillator. I. J. Bifurcation and Chaos 16(1): 207-212 (2006)
- [j12]Kazuki Nakada, Tetsuya Asai, Hatsuo Hayashi: Analog Vlsi Implementation of Resonate-and-fire Neuron. Int. J. Neural Syst. 16(6): 445-456 (2006)
- [c6]Kazuki Nakada, Tetsuya Asai, Hatsuo Hayashi: Burst Synchronization in Two Pulse-Coupled Resonate-and-Fire Neuron Circuits. IFIP PPAI 2006: 285-294
- 2005
- [b1]Andrew Adamatzky, Ben de Lacy Costello, Tetsuya Asai: Reaction-diffusion computers. Elsevier 2005, ISBN 978-0-444-52042-5, pp. I-XIV, 1-334
- [j11]Takahide Oya, Alexandre Schmid, Tetsuya Asai, Yusuf Leblebici, Yoshihito Amemiya: On the fault tolerance of a clustered single-electron neural network for differential enhancement. IEICE Electronic Express 2(3): 76-80 (2005)
- [j10]Tetsuya Hirose, Toshimasa Matsuoka, Kenji Taniguchi, Tetsuya Asai, Yoshihito Amemiya: Ultralow-Power Current Reference Circuit with Low Temperature Dependence. IEICE Transactions 88-C(6): 1142-1147 (2005)
- [j9]Tetsuya Asai, Ben de Lacy Costello, Andrew Adamatzky: Silicon Implementation of a Chemical Reaction-diffusion Processor for Computation of Voronoi Diagram. I. J. Bifurcation and Chaos 15(10): 3307-3320 (2005)
- [j8]Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya: A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. Parallel Algorithms Appl. 20(1): 57-67 (2005)
- [c5]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya: Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ISCAS (3) 2005: 1923-1926
- [c4]Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici: Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. ISCAS (3) 2005: 2535-2538
- 2004
- [j7]Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: A MOS circuit for bursting neural oscillators with excitable oregonators. IEICE Electronic Express 1(4): 73-76 (2004)
- [j6]Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya: Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. IEICE Electronic Express 1(9): 248-252 (2004)
- [c3]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya: An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. ISCAS (3) 2004: 1-4
- 2003
- [j5]Tetsuya Asai, Yusuke Kanazawa, Yoshihito Amemiya: A subthreshold MOS neuron circuit based on the Volterra system. IEEE Transactions on Neural Networks 14(5): 1308-1312 (2003)
- [j4]Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya: An analog CMOS central pattern generator for interlimb coordination in quadruped locomotion. IEEE Transactions on Neural Networks 14(5): 1356-1365 (2003)
- [c2]Tetsuya Asai, Yoshihito Amemiya: Biomorphic Analog Devices based on Reaction-Diffusion Systems. ISMVL 2003: 197-
- 2000
- [j3]Tetsuya Asai, Shinji Hara, Tetsuya Iwasaki: Simultaneous parametric uncertainty modeling and robust control synthesis by LFT scaling. Automatica 36(10): 1457-1467 (2000)
- [c1]Tetsuya Asai, Masato Koutani, Yoshihito Amemiya: An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. IJCNN (3) 2000: 494-499
1990 – 1999
- 1999
- [j2]Tetsuya Asai, Tomoki Fukai, Shigeru Tanaka: A subthreshold MOS circuit for the Lotka-Volterra neural network producing the winners-share-all solution. Neural Networks 12(2): 211-216 (1999)
- 1996
- [j1]Tetsuya Asai, Hideyo Yokotsuka, Tomoki Fukai: A MOS circuit for a nonmonotonic neural network with excellent retrieval capabilities. IEEE Trans. Neural Netw. Learning Syst. 7(1): 182-189 (1996)
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2013-03-13 19:49 CET by the dblp team