| 2013 | ||
|---|---|---|
| j2 | Krit Athikulwongse, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim: Impact of Mechanical Stress on the Full Chip Timing for Through-Silicon-Via-based 3-D ICs. IEEE Trans. on CAD of Integrated Circuits and Systems 32(6): 905-917 (2013) | |
| j1 | Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim: Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout. IEEE Trans. VLSI Syst. 21(5): 862-874 (2013) | |
| c10 | Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, Sung Kyu Lim: Block-level designs of die-to-wafer bonded 3D ICs and their design quality tradeoffs. ASP-DAC 2013: 687-692 | |
| 2012 | ||
| c9 | David Z. Pan, Sung Kyu Lim, Krit Athikulwongse, Moongon Jung, Joydeep Mitra, Jiwoo Pak, Mohit Pathak, Jae-Seok Yang: Design for manufacturability and reliability for TSV-based 3D ICs. ASP-DAC 2012: 750-755 | |
| c8 | Krit Athikulwongse, Mohit Pathak, Sung Kyu Lim: Exploiting die-to-die thermal coupling in 3D IC placement. DAC 2012: 741-746 | |
| c7 | Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim: 3D-MAPS: 3D Massively parallel processor with stacked memory. ISSCC 2012: 188-190 | |
| 2010 | ||
| c6 | Krit Athikulwongse, Xin Zhao, Sung Kyu Lim: Buffered clock tree sizing for skew minimization under power and thermal budgets. ASP-DAC 2010: 474-479 | |
| c5 | Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, Sung Kyu Lim: Design and analysis of 3D-MAPS: A many-core 3D processor with stacked memory. CICC 2010: 1-4 | |
| c4 | Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan: TSV stress aware timing analysis with applications to 3D-IC layout optimization. DAC 2010: 803-806 | |
| c3 | Krit Athikulwongse, Ashutosh Chakraborty, Jae-Seok Yang, David Z. Pan, Sung Kyu Lim: Stress-driven 3D-IC placement with TSV keep-out zone and regularity study. ICCAD 2010: 669-674 | |
| 2009 | ||
| c2 | Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim: A study of Through-Silicon-Via impact on the 3D stacked IC layout. ICCAD 2009: 674-680 | |
| 1997 | ||
| c1 | Sayan Teerapnyawatt, Krit Athikulwongse: An NTSC and PAL closed caption processor. FPL 1997: 374-381 | |
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