Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Daniel Auvergne
2000 – 2009
- 2007
[i1]Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. CoRR abs/0710.4760 (2007)- 2006
- [j6]B. Lasbouygues, Sylvain Engels, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Logical effort model extension to propagation delay representation. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1677-1684 (2006)
- 2005
- [c28]Alexandre Verle, Xavier Michel, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Low Power Oriented CMOS Circuit Optimization Protocol. DATE 2005: 640-645
- 2004
- [c27]Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Delay bound based CMOS gate sizing technique. ISCAS (5) 2004: 189-192
- [c26]Xavier Michel, Alexandre Verle, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Performance Metric Based Optimization Protocol. PATMOS 2004: 100-109
- [c25]B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Temperature Dependence in Low Power CMOS UDSM Process. PATMOS 2004: 110-118
- [c24]A. Landrault, Nadine Azémard, Philippe Maurine, Michel Robert, Daniel Auvergne: Design Optimization with Automated Cell Generation. PATMOS 2004: 722-731
- [c23]B. Lasbouygues, Robin Wilson, Philippe Maurine, Nadine Azémard, Daniel Auvergne: Physical Extension of the Logical Effort Model. PATMOS 2004: 838-848
- 2003
- [j5]Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne: Design Techniques for EEPROMs Embedded in Portable Systems on Chips. IEEE Design & Test of Computers 20(1): 68-75 (2003)
- [c22]Alexandre Verle, Xavier Michel, Philippe Maurine, Nadine Azémard, Daniel Auvergne: CMOS Gate Sizing under Delay Constraint. PATMOS 2003: 60-69
- [c21]Xavier Michel, Alexandre Verle, Nadine Azémard, Philippe Maurine, Daniel Auvergne: Metric Definition for Circuit Speed Optimization. PATMOS 2003: 451-460
- 2002
- [j4]Philippe Maurine, Mustapha Rezzoug, Nadine Azémard, Daniel Auvergne: Transition time modeling in deep submicron CMOS. IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1352-1363 (2002)
- [c20]Philippe Maurine, Xavier Michel, Nadine Azémard, Daniel Auvergne: Gate speed improvement at minimal power dissipation. APCCAS (2) 2002: 325-330
- [c19]W. Rahajandraibe, Christian Dufaza, Daniel Auvergne, B. Cialdella, B. Majoux, V. Chowdhury: Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications. DATE 2002: 316-321
- [c18]Fabrice Picot, Philippe Coll, Daniel Auvergne: Crosstalk Measurement Technique for CMOS ICs. PATMOS 2002: 65-70
- [c17]A. Landrault, L. Pellier, A. Richard, C. Jay, Michel Robert, Daniel Auvergne: Transistor Level Synthesis Dedicated to Fast I.P. Prototyping. PATMOS 2002: 156-166
- [c16]Philippe Maurine, Nadine Azémard, Daniel Auvergne: Structure Independent Representation of Output Transition Time for CMOS Library. PATMOS 2002: 247-257
- 2001
- [j3]Nadine Azémard, Daniel Auvergne: POPS: A tool for delay/power performance optimization. Journal of Systems Architecture 47(3-4): 375-382 (2001)
- [c15]Philippe Maurine, Nadine Azémard, Daniel Auvergne: Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312
- [c14]Nadine Azémard, M. Aline, Philippe Maurine, Daniel Auvergne: Feasible Delay Bound Definition. VLSI-SOC 2001: 325-335
- [c13]Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Output transition time modeling of CMOS structures. ISCAS (5) 2001: 363-366
- [c12]Nadine Azémard, M. Aline, Daniel Auvergne: Delay bound determination for timing closure satisfaction. ISCAS (5) 2001: 375-378
- 2000
- [c11]Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne: Design Techniques for Embedded EEPROM Memories in Portable ASIC and ASSP Solutions. MTDT 2000: 39-46
- [c10]Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne: Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design. PATMOS 2000: 129-138
- [c9]Mustapha Rezzoug, Philippe Maurine, Daniel Auvergne: Second Generation Delay Model for Submicron CMOS Process. PATMOS 2000: 159-167
1990 – 1999
- 1999
- [c8]Augusto Gallegos, Philippe Silvestre, Michel Robert, Daniel Auvergne: RF Interface Design Using Mixed-Mode Methodology. VLSI 1999: 326-333
- [c7]Fernando Moraes, Michel Robert, Daniel Auvergne: A Virtual CMOS Library Approach for East Layout Synthesis. VLSI 1999: 415-426
- 1998
- [j2]S. Turgis, Daniel Auvergne: A novel macromodel for power estimation in CMOS structures. IEEE Trans. on CAD of Integrated Circuits and Systems 17(11): 1090-1098 (1998)
- [c6]Jean Michel Daga, E. Ottaviano, Daniel Auvergne: Temperature Effect on Delay for Low Voltage Applications. DATE 1998: 680-685
- 1997
- [c5]S. Turgis, Jean Michel Daga, J. M. Portal, Daniel Auvergne: Internal power modelling and minimization in CMOS inverters. ED&TC 1997: 603-608
- 1995
- [c4]Jean Michel Daga, Michel Robert, Daniel Auvergne: Delay modelling improvement for low voltage applications. EURO-DAC 1995: 216-221
- [c3]S. Turgis, Nadine Azémard, Daniel Auvergne: Explicit evaluation of short circuit power dissipation for CMOS logic structures. ISLPD 1995: 129-134
- 1994
- [c2]Michel Robert, Lionel Torres, Fernando Moraes, Daniel Auvergne: Influence of Locig Block Layout Architecture on FPGA Performance. FPL 1994: 34-44
- 1993
- [j1]Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne: Post-layout timing simulation of CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1170-1177 (1993)
- 1990
- [c1]Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne: Path runner: an accurate and fast timing analyser. EURO-DAC 1990: 529-533
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-12-02 20:48 CET by the dblp team