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 | 2013 | |
|---|---|---|
| c22 |      | Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal, Ahsan Raja Chowdhury: Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. VLSI Design 2013: 103-108 |
| c21 | | Md. Shamsujjoha, Hafiz Md. Hasan Babu: A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors. VLSI Design 2013: 368-373 |
| 2012 | ||
| c20 | | Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu: An efficient approach for designing and minimizing reversible programmable logic arrays. ACM Great Lakes Symposium on VLSI 2012: 215-220 |
| c19 | | Lafifa Jamal, Md. Masbaul Alam Polash, M. A. Mottalib, Hafiz Md. Hasan Babu: On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits. VDAT 2012: 281-288 |
| 2011 | ||
| c18 | | Ankur Sarker, Tanvir Ahmed, S. M. Mahbubur Rashid, Shahed Anwar, Lafifa Jamal, Nazma Tara, Md. Masbaul Alam, Hafiz Md. Hasan Babu: Realization of Reversible Logic in DNA Computing. BIBE 2011: 261-265 |
| 2010 | ||
| c17 | | Irina Hashmi, Hafiz Md. Hasan Babu: An Efficient Design of a Reversible Barrel Shifter. VLSI Design 2010: 93-98 |
| i5 | | Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam, Hafiz Md. Hasan Babu: Efficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing. CoRR abs/1008.3320 (2010) |
| i4 | | Md. Rafiqul Islam, Md. Saiful Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Hafiz Md. Hasan Babu: Variable Block Carry Skip Logic using Reversible Gates. CoRR abs/1008.3352 (2010) |
| i3 | | Hafiz Md. Hasan Babu, Md. Saiful Islam, Md. Rafiqul Islam, Lafifa Jamal, Abu Ahmed Ferdaus, Muhammad Rezaul Karim, Abdullah Al Mahmud: Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings. CoRR abs/1008.3357 (2010) |
| i2 | | Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam, Hafiz Md. Hasan Babu: Wrapper/TAM Co-Optimization and Test Scheduling for SOCs Using Rectangle Bin Packing Considering Diagonal Length of Rectangles. CoRR abs/1008.4446 (2010) |
| i1 | | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Muhammad Rezaul Karim, Abdullah Al Mahmud, Md. Saiful Islam: Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing. CoRR abs/1008.4448 (2010) |
| 2008 | ||
| j2 | | Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: Efficient approaches for designing reversible Binary Coded Decimal adders. Microelectronics Journal 39(12): 1693-1703 (2008) |
| c16 | | Muhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: Minimization of CTS of k-CNOT Circuits for SSF and MSF Model. DFT 2008: 290-298 |
| c15 | | Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu: A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. VLSI Design 2008: 566-571 |
| 2006 | ||
| j1 | | Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Design of a compact reversible binary coded decimal adder circuit. Journal of Systems Architecture 52(5): 272-282 (2006) |
| c14 |  | Amin Ahsan Ali, Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. CDES 2006: 101-106 |
| c13 | | Ahsan Raja Chowdhury, Rumana Nazmul, Hafiz Md. Hasan Babu: A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. VLSI Design 2006: 311-316 |
| 2005 | ||
| c12 | | Md. Sumon Shahriar, A. R. Mustafa, Chowdhury Farhan Ahmed, Abu Ahmed Ferdaus, A. N. M. Zaheduzzaman, Shahed Anwar, Hafiz Md. Hasan Babu: An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. DSD 2005: 122-126 |
| c11 | | Hafiz Md. Hasan Babu, Ahsan Raja Chowdhury: Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. VLSI Design 2005: 255-260 |
| 2004 | ||
| c10 | | Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam: Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. DSD 2004: 603-606 |
| c9 | | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Rumana Nazmul, Md. Anwarul Haque, Ahsan Raja Chowdhury: A heuristic approach to synthesize Boolean functions using TANT network. ISCAS (2) 2004: 373-376 |
| c8 | | Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Rafiqul Islam, Md. Mazder Rahman: On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. ISMVL 2004: 321-326 |
| c7 | | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury: Synthesis of Full-Adder Circuit Using Reversible Logic. VLSI Design 2004: 757-760 |
| 2003 | ||
| c6 | | Md. Rafiqul Islam, Hafiz Md. Hasan Babu, Mohammad Abdur Rahim Mustafa, Md. Sumon Shahriar: A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. Asian Test Symposium 2003: 90-95 |
| c5 | | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury: Reversible Logic Synthesis for Minimization of Full-Adder Circuit. DSD 2003: 50-54 |
| c4 | | Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Amin Ahsan Ali, Mohammad Musa Salehin Akon: A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. ISMVL 2003: 111-116 |
| 2000 | ||
| c3 | | Hafiz Md. Hasan Babu, Tsutomu Sasao: Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. ISMVL 2000: 147-152 |
| 1999 | ||
| c2 | | Hafiz Md. Hasan Babu, Tsutomu Sasao: Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. ISMVL 1999: 166-172 |
| 1998 | ||
| c1 | | Hafiz Md. Hasan Babu, Tsutomu Sasao: Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. ISMVL 1998: 45-51 |
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