Mustafa Badaroglu

Mustafa Badaroglu, Ugur Halici, Isik Aybay, Cuneyt Cerkez: A Cascadable Random Neural Network Chip with Reconfigurable Topology. Comput. J. 53(3): 289-303 (2010)

Mustafa Badaroglu, Guy Decabooter, Francois Laulanet, Olivier Charlier: Calibration of Integrated CMOS Hall Sensors Using Coil-on-Chip in ATE Environment. DATE 2008: 873-878

Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Scalable Gate-Level Models for Power and Timing Analysis. ISCAS 2007: 2938-2941

Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke: Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers. VTC Spring 2007: 3135-3139

Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke: Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling. EURASIP J. Wireless Comm. and Networking 2006 (2006)

Mustafa Badaroglu, Kris Tiri, Geert Van der Plas, Piet Wambacq, Ingrid Verbauwhede, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1146-1154 (2006)

Mustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: SWAN: high-level simulation methodology for digital substrate noise generation. IEEE Trans. VLSI Syst. 14(1): 23-33 (2006)

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital ground bounce reduction by supply current shaping and clock frequency Modulation. IEEE Trans. on CAD of Integrated Circuits and Systems 24(1): 65-76 (2005)

Geert Van der Plas, Mustafa Badaroglu, Gerd Vandersteen, Petr Dobrovolný, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects. DAC 2004: 854-859

Mustafa Badaroglu, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man: Digital Ground Bounce Reduction by Phase Modulation of the Clock. DATE 2004: 88-93

Mustafa Badaroglu, Kris Tiri, Stéphane Donnay, Piet Wambacq, Hugo De Man, Ingrid Verbauwhede, Georges G. E. Gielen: Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients. DAC 2002: 399-404

Mustafa Badaroglu, Marc van Heijningen, Vincent Gravot, Stéphane Donnay, Hugo De Man, Georges G. E. Gielen, Marc Engels, Ivo Bolsens: High-level simulation of substrate noise generation from large digital circuits with multiple supplies. DATE 2001: 326-330

Marc van Heijningen, Mustafa Badaroglu, Stéphane Donnay, Marc Engels, Ivo Bolsens: High-level simulation of substrate noise generation including power supply noise coupling. DAC 2000: 446-451