Jean-Loup Baer

Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney: Memory Hierarchy Design for a Multiprocessor Look-up Engine. IEEE PACT 2003: 206-216

Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer, Mateo Valero: Cost-Effective Compiler Directed Memory Prefetching and Bypassing. IEEE PACT 2002: 189-198

Wayne A. Wong, Jean-Loup Baer: Modified LRU Policies for Improving Second-Level Cache Behavior. HPCA 2000: 49-60

Patrick Crowley, Marc E. Fiuczynski, Jean-Loup Baer, Brian N. Bershad: Characterizing processor architectures for programmable network interfaces. ICS 2000: 54-65

Peter van Vleet, Eric J. Anderson, Lindsay Brown, Jean-Loup Baer, Anna R. Karlin: Pursuing the Performance Potential of Dynamic Cache Line Sizes. ICCD 1999: 528-537

Patrick Crowley, Jean-Loup Baer: On the Use of Trace Sampling for Architectural Studies of Desktop Applications. SIGMETRICS 1999: 208-209

Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Thomas E. Anderson, Brian N. Bershad: Execution Characteristics of Desktop Applications on Windows NT. ISCA 1998: 27-38

Jean-Loup Baer, Wen-Hann Wang: Retrospective: On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints 1998: 59-60

Jean-Loup Baer, Wen-Hann Wang: On the Inclusion Properties for Multi-Level Cache Hierarchies. 25 Years ISCA: Retrospectives and Reprints 1998: 345-352

Xiaohan Qin, Jean-Loup Baer: Optimizing Software Cache-coherent Cluster Architectures. SC 1998: 25

Xiaohan Qin, Jean-Loup Baer: On the Use and Performance of Explicit Communication Primitives in Cache-Coherent Multiprocessor Systems. HPCA 1997: 182-193

Xiaohan Qin, Jean-Loup Baer: A Performance Evaluation of Cluster-Based Architectures. SIGMETRICS 1997: 237-247

Theodore H. Romer, Dennis Lee, Geoffrey M. Voelker, Alec Wolman, Wayne A. Wong, Jean-Loup Baer, Brian N. Bershad, Henry M. Levy: The Structure and Performance of Interpreters. ASPLOS 1996: 150-159

Jean-Loup Baer (Ed.): Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996. ACM 1996, isbn 0-89791-786-3

Tien-Fu Chen, Jean-Loup Baer: Effective Hardware Based Data Prefetching for High-Performance Processors. IEEE Trans. Computers 44(5): 609-623 (1995)

Xiaohan Qin, Jean-Loup Baer: A comparative study of conservative and optimistic trace-driven simulations. Annual Simulation Symposium 1995: 42-50

Craig Anderson, Jean-Loup Baer: Two Techniques for Improving Performance on Bus-Based Multiprocessors. HPCA 1995: 264-275

Dennis Lee, Jean-Loup Baer, Brad Calder, Dirk Grunwald: Instruction Cache Fetch Policies for Speculative Execution. ISCA 1995: 357-367

Sang Lyul Min, Jae H. Nam, Myung Soon Park, Jean-Loup Baer: Cache-Based Data Distribution Constrained Scheduling. International Journal of High Speed Computing 6(1): 139-155 (1994)

Jean-Loup Baer, Tien-Fu Chen: An Evaluation of Hardware and Software Data Prefetching. Applications in Parallel and Distributed Computing 1994: 257-266

Richard N. Zucker, Jean-Loup Baer: Software versus Hardware Coherence: Performance versus Cos. HICSS (1) 1994: 163-172

Xiaohan Qin, Jean-Loup Baer: A Parallel Trace-driven Simulator: Implementation and Performance. ICPP 1994: 314-318

Tien-Fu Chen, Jean-Loup Baer: A Performance Study of Software and Hardware Data Prefetching Schemes. ISCA 1994: 223-232

Craig Anderson, Jean-Loup Baer: A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors. IPPS 1993: 142-148

Sang Lyul Min, Jean-Loup Baer: Design and Analysis of a Scalable Cache Coherence Scheme Based on Clocks and Timestamps. IEEE Trans. Parallel Distrib. Syst. 3(1): 25-44 (1992)

Tien-Fu Chen, Jean-Loup Baer: Reducing Memory Latency via Non-blocking and Prefetching Caches. ASPLOS 1992: 51-61

Richard N. Zucker, Jean-Loup Baer: A Performance Study of Memory Consistency Models. ISCA 1992: 2-12

Wen-Hann Wang, Jean-Loup Baer: Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. ACM Trans. Comput. Syst. 9(3): 222-241 (1991)

Jean-Loup Baer, Richard N. Zucker: On Synchronization Patterns in Parallel Programs. ICPP (2) 1991: 60-67

Jean-Loup Baer, Tien-Fu Chen: An effective on-chip preloading scheme to reduce data access penalty. SC 1991: 176-186

Sang Lyul Min, Jean-Loup Baer: A Performance Comparison of Directory-based and Timestamp-based Cache Coherence Schemes. ICPP (1) 1990: 305-311

Sang Lyul Min, Jean-Loup Baer, Hyoung-Joo Kim: An efficient caching support for critical sections in large-scale shared-memory multiprocessors. ICS 1990: 34-47

Wen-Hann Wang, Jean-Loup Baer: Efficient Trace-Driven Simulation Methods for Cache Performance Analysis. SIGMETRICS 1990: 27-36

Jean-Loup Baer, Larry Snyder, James R. Goodman (Eds.): Proceedings of the 17th Annual International Symposium on Computer Architecture. Seattle, WA, June 1990. ACM 1990, isbn 0-89791-366-3

Jean-Loup Baer, Wen-Hann Wang: Multilevel Cache Hierarchies: Organizations, Protocols, and Performance. J. Parallel Distrib. Comput. 6(3): 451-476 (1989)

Jean-Loup Baer, Yi-Bing Lin: Improving Quicksort Performance with a Codewort Data Structure. IEEE Trans. Software Eng. 15(5): 622-631 (1989)

Sang Lyul Min, Jean-Loup Baer: A Timestamp-based Cache Coherence Scheme. ICPP (1) 1989: 23-32

Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan: Extending the Memory Hierarchy into Multiprocessor Interconnection Networks: A Performance Analysis. ICPP (1) 1989: 41-50

Wen-Hann Wang, Jean-Loup Baer, Henry M. Levy: Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy. ISCA 1989: 140-148

Haim E. Mizrahi, Jean-Loup Baer, Edward D. Lazowska, John Zahorjan: Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks. ISCA 1989: 158-166

Jean-Loup Baer, Meei-Chiueh Liem, Larry McMurchie, Rudolf Nottrott, Lawrence Snyder, Wayne Winder: A Notation for Describing Multiple Views of VLSI Circuits. DAC 1988: 102-107

Jean-Loup Baer, Wen-Hann Wang: On the Inclusion Properties for Multi-Level Cache Hierarchies. ISCA 1988: 73-80

Jean-Loup Baer, Wen-Hann Wang: Architectural Choices for Multi-level Cache Hierarchies. ICPP 1987: 258-261

James K. Archibald, Jean-Loup Baer: Cache Coherence Protocols: Evaluation Using a Multiprocessor Simulation Model. ACM Trans. Comput. Syst. 4(4): 273-298 (1986)

Jean-Loup Baer: Modelling Architectural Features with Petri Nets. Advances in Petri Nets 1986: 258-277

Sai Choi Kwan, Jean-Loup Baer: The I/O Performance of Multiway Mergesort and Tag Sort. IEEE Trans. Computers 34(4): 383-387 (1985)

Sai Choi Kwan, Jean-Loup Baer, G. Zick, T. Snyder: Parallel Tag-Distribution Sort. ICPP 1985: 854-861

Jean-Loup Baer: Computer Architecture. IEEE Computer 17(10): 77-87 (1984)

James K. Archibald, Jean-Loup Baer: An Economical Solution to the Cache Coherence Problem. ISCA 1984: 355-362

Jean-Loup Baer, Hung-Chang Du, Richard E. Ladner: Binary Search in a Multiprocessing Environment. IEEE Trans. Computers 32(7): 667-677 (1983)

Hung-Chang Du, Jean-Loup Baer: On the Performance of Interleaved Memories with Non-Uniform Access Probabilities. ICPP 1983: 429-436

Harold W. Lawson Jr., Tilak Agerwala, Hans H. Heilborn, Hideo Aiso, Lars-Erik Thorelli, Jean-Loup Baer, Mario Tokoro (Eds.): Proceedings of the 10th Annual Symposium on Computer Architecture, 1983. ACM 1983, isbn 0-89791-101-6

Ahmed S. Zaki, Jean-Loup Baer: Query costs in HB(1) trees versus 2-3 trees. International Journal of Parallel Programming 10(6): 383-395 (1981)

Jean-Loup Baer, Georges Gardarin, Claude Girault, Gérard Roucairol: The Two-Step Commitment Protocol: Modeling, Specification and Proof Methodology. ICSE 1981: 363-373

Jean-Loup Baer, Barbara Koyama: On the Minimization of the Width of the Control Memory of Microprogammed Processors. IEEE Trans. Computers 28(4): 330-316 (1979)

Jean-Loup Baer, B. Schwab: A Comparison of Tree-Balancing Algorithms. Commun. ACM 20(5): 322-330 (1977)

Jean-Loup Baer, Carla Schlatter Ellis: Model, Design, and Evaluation of a Compiler for a Parallel Processing Environment. IEEE Trans. Software Eng. 3(6): 394-405 (1977)

Jean-Loup Baer, M. Fries: On the Efficiency of Some List Marketing Algorithms. IFIP Congress 1977: 751-756

Jean-Loup Baer, John E. Jensen: Simulation of Large Parallel Systems: Modelling of Tasks. Performance 1977: 53-73

G. Kampen, Jean-Loup Baer: The Formal Definition of Semantics by String Automata. Comput. Lang. 1(2): 121-138 (1976)

Jean-Loup Baer: Multiprocessing Systems. IEEE Trans. Computers 25(12): 1271-1277 (1976)

Jean-Loup Baer, Gary R. Sager: Dynamic Improvement of Locality in Virtual Memory Systems. IEEE Trans. Software Eng. 2(1): 54-62 (1976)

Jean-Loup Baer, Gary R. Sager: Correction to "Dynamic Improvement of Locality in Virtual Memory Systems". IEEE Trans. Software Eng. 2(2): 137 (1976)

John E. Jensen, Jean-Loup Baer: A Model of Interference in a Shared Resource Multiprocessor. ISCA 1976: 52-57

Jean-Loup Baer: Weight-balanced trees. AFIPS National Computer Conference 1975: 467-472

Jean-Loup Baer: A Survey of Some Theoretical Aspects of Multiprocessing. ACM Comput. Surv. 5(1): 31-80 (1973)

Jean-Loup Baer, Robert Caughey: Segmentation and optimization of programs from cyclic structure analysis. AFIPS Spring Joint Computing Conference 1972: 23-36

Jean-Loup Baer, Daniel P. Bovet, Gerald Estrin: Legality and Other Properties of Graph Models of Computations. J. ACM 17(3): 543-554 (1970)

Jean-Loup Baer, Daniel P. Bovet: Compilation of arithmetic expressions for parallel computations. IFIP Congress (1) 1968: 340-346