Nader Bagherzadeh

H. Sarbazi-Azad, Nader Bagherzadeh: Multicore computing systems: Architecture, programming tools, and applications. J. Comput. Syst. Sci. 79(4): 403-405 (2013)

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh: Scalable load balancing congestion-aware Network-on-Chip router architecture. J. Comput. Syst. Sci. 79(4): 421-439 (2013)

Ayhan Demiriz, Nader Bagherzadeh, Abdulaziz Alhussien: CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture. PDP 2013: 486-493

Azadeh Eskandari, Ahmad Khademzadeh, Nader Bagherzadeh, Majid Janidarmian: Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm. PDP 2013: 504-508

W.-H. Hu, C.-Y. Chen, Jun Ho Bahn, Nader Bagherzadeh: Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform. IET Computers & Digital Techniques 6(2): 86-94 (2012)

Abdulaziz Alhussien, Chifeng Wang, Nader Bagherzadeh: Design and evaluation of a high throughput robust router for network-on-chip. IET Computers & Digital Techniques 6(3): 173-179 (2012)

Chifeng Wang, Nader Bagherzadeh: High-throughput differentiated service provision router architecture for wireless network-on-chip. IJHPSA 4(1): 38-56 (2012)

Freddy Bolanos, Jose Edison Aedo, Fredy Rivera, Nader Bagherzadeh: Mapping and Scheduling in Heterogeneous NoC through Population-Based Incremental Learning. J. UCS 18(7): 901-916 (2012)

Hamid Sarbazi-Azad, Nader Bagherzadeh: Editorial notes: Special issue on on-chip parallel and network-based systems. Microprocessors and Microsystems - Embedded Hardware Design 36(7): 529-530 (2012)

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh: A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. Microprocessors and Microsystems - Embedded Hardware Design 36(7): 555-570 (2012)

Chifeng Wang, Nader Bagherzadeh: Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip. PDP 2012: 457-464

Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh: Design and Analysis of a Mesh-based Wireless Network-on-Chip. PDP 2012: 483-490

Sanaz Azampanah, Ahmad Khademzadeh, Nader Bagherzadeh, Majid Janidarmian, Reza Shojaee: LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC. PDP 2012: 515-519

Abdulaziz Alhussien, Nader Bagherzadeh, Freek Verbeek, Bernard van Gastel, Julien Schmaltz: A formally verified deadlock-free routing function in a fault-tolerant NoC architecture. SBCCI 2012: 1-6

Akira Hatanaka, Nader Bagherzadeh: A scheduling approach for distributed resource architectures with scarce communication resources. IJHPSA 3(1): 12-22 (2011)

Nader Bagherzadeh, Hamid Sarbazi-Azad: Special issue on: On-chip parallel and network-based systems. Journal of Systems Architecture - Embedded Systems Design 57(1): 1-3 (2011)

Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh: Area and power-efficient innovative congestion-aware Network-on-Chip architecture. Journal of Systems Architecture - Embedded Systems Design 57(1): 24-38 (2011)

Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh: A Wireless Network-on-Chip Design for Multicore Platforms. PDP 2011: 409-416

Jungsook Yang, Chuny Chun, Nader Bagherzadeh, Seung Eun Lee: Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform. PDP 2011: 439-446

Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Jungsook Yang, Nader Bagherzadeh: Parallel processing for block ciphers on a fault tolerant networked processor array. IJHPSA 2(3/4): 156-167 (2010)

Frank Penczek, Stephan Herhut, Sven-Bodo Scholz, Alexander V. Shafarenko, Jungsook Yang, Chun-Yi Chen, Nader Bagherzadeh, Clemens Grelck: Message Driven Programming with S-Net: Methodology and Performance. ICPP Workshops 2010: 405-412

Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh: Area and Power-efficient Innovative Network-on-Chip Architecurte. PDP 2010: 533-539

Radha Guha, Nader Bagherzadeh, Pai H. Chou: Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system. Computers & Electrical Engineering 35(2): 258-285 (2009)

Seung Eun Lee, Nader Bagherzadeh: A high level power model for Network-on-Chip (NoC) router. Computers & Electrical Engineering 35(6): 837-845 (2009)

Faruk Bagci, Florian Kluge, Theo Ungerer, Nader Bagherzadeh: Optimisations for LocSens - an indoor location tracking system using wireless sensors. IJSNet 6(3/4): 157-166 (2009)

Seung Eun Lee, Nader Bagherzadeh: A variable frequency link for a power-aware network-on-chip (NoC). Integration 42(4): 479-485 (2009)

Jun Ho Bahn, Jungsook Yang, Wen-Hsiang Hu, Nader Bagherzadeh: Parallel FFT Algorithms on Network-on-Chips. Journal of Circuits, Systems, and Computers 18(2): 255-269 (2009)

Nader Bagherzadeh, Masaru Matsuura: Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip. Journal of Circuits, Systems, and Computers 18(2): 283-294 (2009)

Marcos Sanchez-Elez, Nader Bagherzadeh, Román Hermida: A framework for low energy data management in reconfigurable multi-context architectures. Journal of Systems Architecture - Embedded Systems Design 55(2): 127-139 (2009)

Faruk Bagci, Julian Wolf, Theo Ungerer, Nader Bagherzadeh: Mobile Agents for Wireless Sensor Networks. ICWN 2009: 502-508

Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh: Low power adaptive pipeline based on instruction isolation. ISQED 2009: 788-793

Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh: Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. ITNG 2009: 849-854

Akira Hatanaka, Nader Bagherzadeh: Scheduling Techniques for Multi-Core Architectures. ITNG 2009: 865-870

Wen-Hsiang Hu, Jun Ho Bahn, Nader Bagherzadeh: Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. SBAC-PAD 2009: 35-40

Jun Ho Bahn, Nader Bagherzadeh: Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. IET Computers & Digital Techniques 2(1): 63-73 (2008)

Fredy Rivera, Marcos Sanchez-Elez, Román Hermida, Nader Bagherzadeh: Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. IET Computers & Digital Techniques 2(3): 199-213 (2008)

Nozar Tabrizi, Nader Bagherzadeh: An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator. Integration 41(1): 65-75 (2008)

Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh: On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. Parallel Processing Letters 18(2): 239-255 (2008)

Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh: A Generic Network Interface Architecture for a Networked Processor Array (NePA). ARCS 2008: 247-260

Hala Elsadek, Hesham Eldeeb, Haytham Abdallah, Maha Eldesouky, Nader Bagherzadeh: Specific Absorption Rate Calculation using Parallel 3D Finite Difference Time Domain Technique. Communications in Computing 2008: 153-159

Faruk Bagci, Florian Kluge, Nader Bagherzadeh, Theo Ungerer: LocSens - An Indoor Location Tracking System using Wireless Sensors. ICCCN 2008: 887-891

Faruk Bagci, Theo Ungerer, Nader Bagherzadeh: ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks. ICWN 2008: 3-9

Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh: Parallel FFT Algorithms on Network-on-Chips. ITNG 2008: 1087-1093

Nader Bagherzadeh, Masaru Matsuura: Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip. ITNG 2008: 1101-1106

Afshin Niktash, Hooman Parizi, Amir Hosein Kamalizad, Nader Bagherzadeh: RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding. WCNC 2008: 605-610

Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh: Design of a router for network-on-chip. IJHPSA 1(2): 98-105 (2007)

Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou: Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling. ACM Trans. Design Autom. Electr. Syst. 12(4) (2007)

Afshin Niktash, Hooman Parizi, Nader Bagherzadeh: A Reconfigurable Processor for Forward Error Correction. ARCS 2007: 1-13

Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou: Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost. ASP-DAC 2007: 872-877

Fredy Rivera, Marcos Sanchez-Elez, Nader Bagherzadeh: Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures. ERSA 2007: 85-91

Akira Hatanaka, Nader Bagherzadeh: A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template. IPDPS 2007: 1-8

Afshin Niktash, Hooman Parizi, Nader Bagherzadeh: Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems. ISCAS 2007: 2586-2589

Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh: On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. ITNG 2007: 1033-1038

Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh: Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). SBAC-PAD 2007: 211-218

Seung Eun Lee, Nader Bagherzadeh: Increasing the throughput of an adaptive router in network-on-chip (NoC). CODES+ISSS 2006: 82-87

Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sanchez-Elez, Nader Bagherzadeh, Fredy Rivera: Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys). DATE Designers' Forum 2006: 52-57

Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh: Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. FPL 2006: 1-8

Hooman Parizi, Afshin Niktash, Amir Hosein Kamalizad, Nader Bagherzadeh: A Reconfigurable Architecture for Wireless Communication Systems. ITNG 2006: 250-255

Afshin Niktash, Hooman Parizi, Nader Bagherzadeh: A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture. VTC Fall 2006: 1-5

Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh, Akira Hatanaka: A Programmable DSP Architecture for Wireless Communication Systems. ASAP 2005: 231-238

Fredy Rivera, Milagros Fernández, Nader Bagherzadeh: An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. DSD 2005: 396-402

Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh: Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. IPDPS 2005

Nader Bagherzadeh, Mateo Valero, Alex Ramírez (Eds.): Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005. ACM 2005, isbn 1-59593-018-3

Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David Jensen: Fast and efficient voltage scheduling by evolutionary slack distribution. ASP-DAC 2004: 659-662

Nozar Tabrizi, Nader Bagherzadeh, Amir Hosein Kamalizad, Haitao Du: MaRS: a macro-pipelined reconfigurable system. Conf. Computing Frontiers 2004: 343-349

Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh: Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. CODES+ISSS 2004: 30-35

Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou: An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. ISLPED 2004: 381-386

Amir Hosein Kamalizad, Richard Plettner, Chengzhi Pan, Nader Bagherzadeh: Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform. SoCC 2004: 3-6

Marcos Sanchez-Elez, Haitao Du, Nozar Tabrizi, Yun Long, Nader Bagherzadeh, Milagros Fernández: Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture. Computers & Graphics 27(5): 701-713 (2003)

Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes: Automatic compilation to a coarse-grained reconfigurable system-opn-chip. ACM Trans. Embedded Comput. Syst. 2(4): 560-589 (2003)

Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott: Adaptive computing: what can it do, where can it go? ASP-DAC 2003: 463

Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel Lois Anido, Milagros Fernández: Interactive ray tracing on reconfigurable SIMD MorphoSys. ASP-DAC 2003: 471-476

Dexin Li, Pai H. Chou, Nader Bagherzadeh: Topology selection for energy minimization in embedded networks. ASP-DAC 2003: 693-696

Arezou Koohi, Nader Bagherzadeh, Chengzi Pan: A fast parallel reed-solomon decoder on a reconfigurable architecture. CODES+ISSS 2003: 59-64

Marcos Sanchez-Elez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida: Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. DATE 2003: 10036-10043

Chengzhi Pan, Nader Bagherzadeh, Amir Hosein Kamalizad, Arezou Koohi: Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. DATE 2003: 10468-10475

Haitao Du, Marcos Sanchez-Elez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández: Interactive Ray Tracing on Reconfigurable SIMD MorphoSys. DATE 2003: 20144-20149

Alexander Paar, Haitao Du, Nader Bagherzadeh: A Component Oriented Simulator for HW/SW Co-Designs. ESTImedia 2003: 79-86

Miguel Sainz, Antonio Susin, Nader Bagherzadeh: Camera calibration of long image sequences with the presence of occlusions. ICIP (1) 2003: 317-320

Amir Hosein Kamalizad, Chengzhi Pan, Nader Bagherzadeh: Fast Parallel FFT on a Reconfigurable Computation Platform. SBAC-PAD 2003: 254-259

Pai H. Chou, Jinfeng Liu, Dexin Li, Nader Bagherzadeh: IMPACCT: Methodology and Tools for Power-Aware Embedded Systems. Design Autom. for Emb. Sys. 7(3): 205-232 (2002)

Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh: Communication speed selection for embedded systems with networked voltage-scalable processors. CODES 2002: 169-174

Marcos Sanchez-Elez, Milagros Fernández, Rafael Maestre, Román Hermida, Nader Bagherzadeh, Fadi J. Kurdahi: A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. DATE 2002: 547-552

Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh: Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. DSD 2002: 148-155

Alexander Paar, Manuel L. Anido, Nader Bagherzadeh: A Novel Predication Scheme for a SIMD System-on-Chip. Euro-Par 2002: 834-843

Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi: MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note). Euro-Par 2002: 844-848

Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu: Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors. ISSS 2002: 14-19

Miguel Sainz, Nader Bagherzadeh, Antonio Susin: Recovering 3D Metric Structure and Motion from Multiple Uncalibrated Cameras. ITCC 2002: 268-273

Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh: Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources. PACS 2002: 84-98

Manuel L. Anido, Nader Bagherzadeh, Nozar Tabrizi, Haitao Du, Marcos Sanchez-Elez: Interactive Ray Tracing Using a SIMD Reconfigurable Architecture. SBAC-PAD 2002: 20-28

Dexin Li, Pai H. Chou, Nader Bagherzadeh: Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. VLSI Design 2002: 697-704

Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh: Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. Journal of Systems Architecture 47(3-4): 277-292 (2001)

Rafael Maestre, F. Kurdahl, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh: A formal approach to context scheduling for multicontext reconfigurable architectures. IEEE Trans. VLSI Syst. 9(1): 173-185 (2001)

Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Román Hermida, Nader Bagherzadeh, Hartej Singh: A framework for reconfigurable computing: task scheduling and context management. IEEE Trans. VLSI Syst. 9(6): 858-873 (2001)

Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm: A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. CASES 2001: 116-125

Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi: A constraint-based application model and scheduling techniques for power-aware systems. CODES 2001: 153-158

Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi: Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. DAC 2001: 840-845

Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh: A data scheduler for multi-context reconfigurable architectures. ISSS 2001: 177-182

Fadi J. Kurdahi, Nader Bagherzadeh, Peter Athanas, Jose L. Muñoz: Guest Editors' Introduction: Configurable Computing. IEEE Design & Test of Computers 17(1): 17-19 (2000)

Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh, Eliseu M. Chaves Filho: MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. IEEE Trans. Computers 49(5): 465-481 (2000)

Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves: Design and Implementation of the MorphoSys Reconfigurable Computing Processor. VLSI Signal Processing 24(2-3): 147-164 (2000)

Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh: MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. DAC 2000: 573-578

Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh: Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. FCCM 2000: 297-298

Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh: Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. ICCD 2000: 575-576

Rafael Maestre, Fadi J. Kurdahi, Milagros Fernández, Nader Bagherzadeh, Hartej Singh: Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. ISSS 2000: 107-114

Rafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández: Kernel Scheduling in Reconfigurable Computing. DATE 1999: 90-96

Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves: The MorphoSys Dynamically Reconfigurable System-on-Chip. Evolvable Hardware 1999: 152-160

Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho: The MorphoSys Parallel Reconfigurable System. Euro-Par 1999: 727-734

Guangming Lu, Ming-Hau Lee, Hartej Singh, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho: MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application. IPPS/SPDP Workshops 1999: 661-669

Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh: A Framework for Scheduling and Context Allocation in Reconfigurable Computing. ISSS 1999: 134-140

S. Shoari, Nader Bagherzadeh, D. Goodman, Thomas E. Milner, D. J. Smithies, J. S. Nelson: A parallel algorithm for pulsed laser infrared tomography. Pattern Recognition Letters 19(5-6): 521-526 (1998)

Nader Bagherzadeh, Martin Dowd, Shahram Latifi: Faster column operations in star networks. Telecommunication Systems 10(1): 33-44 (1998)

Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi: Low Expansion Packings and Embeddings of Hypercubes into Star Graphs: A Performance-Oriented Approach. IEEE Trans. Parallel Distrib. Syst. 9(3): 261-274 (1998)

Steven Wallace, Nader Bagherzadeh: Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors. IEEE Trans. Parallel Distrib. Syst. 9(6): 570-578 (1998)

Shahram Latifi, Nader Bagherzadeh: On Embedding Rings into a Star-Related Network. Inf. Sci. 99(1-2): 21-35 (1997)

Steven Wallace, Nader Bagherzadeh: Multiple Branch and Block Prediction. HPCA 1997: 94-103

Marcelo M. de Azevedo, Nader Bagherzadeh, Martin Dowd, Shahram Latifi: Some Topological Properties of Star Connected Cycles. Inf. Process. Lett. 58(2): 81-85 (1996)

Nayla Nassif, Nader Bagherzadeh: A Grid Embedding into the Star Graph for Image Analysis Solutions. Inf. Process. Lett. 60(5): 255-260 (1996)

Nader Bagherzadeh, Martin Dowd, Nayla Nassif: Embedding an Arbitrary Binary Tree into the Star Graph. IEEE Trans. Computers 45(4): 475-481 (1996)

M. Loikkanen, Nader Bagherzadeh: A fine-grain multithreading superscalar architecture. IEEE PACT 1996: 163-168

Steven Wallace, Nader Bagherzadeh: A scalable register file architecture for dynamically scheduled processors. IEEE PACT 1996: 179-184

Marcelo Moraes de Azevdeo, Nader Bagherzadeh, Shahram Latifi: Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing. Euro-Par, Vol. I 1996: 247-252

Steven Wallace, Nader Bagherzadeh: Instruction Fetching Mechanisms for Superscalar Microprocessors. Euro-Par, Vol. II 1996: 747-756

Manu Gulati, Nader Bagherzadeh: Performance Study of a Multithreaded Superscalar Microprocessor. HPCA 1996: 291-301

Shahram Latifi, Nader Bagherzadeh: Hamiltonicity of the Clustered-Star Graph with Embedding Applications. PDPTA 1996: 734-744

Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi: Broadcasting Algorithms for the Star-Connected Cycles Interconnection Network. J. Parallel Distrib. Comput. 25(2): 209-222 (1995)

Nader Bagherzadeh, Martin Dowd, Shahram Latifi: A Well-Behaved Enumeration of Star Graphs. IEEE Trans. Parallel Distrib. Syst. 6(5): 531-535 (1995)

Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi: Fault-diameter of the star-connected cycles interconnection network. HICSS (2) 1995: 469-478

Steven Wallace, Nirav Dagli, Nader Bagherzadeh: Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. ICCD 1995: 96-101

Alireza Kavianpour, Nader Bagherzadeh: Parallel Algorithms for Line Detection on A Pyramid Architecture. IJPRAI 8(1): 337-349 (1994)

S. Shoari, Alireza Kavianpour, Nader Bagherzadeh: Pyramid simulation of image processing applications. Image Vision Comput. 12(8): 523-529 (1994)

Alireza Kavianpour, S. Shoari, Nader Bagherzadeh: A New Approach for Circle Detection on Multiprocessors. J. Parallel Distrib. Comput. 20(2): 256-260 (1994)

Shahram Latifi, Nader Bagherzadeh: Incomplete Star: An Incrementally Scalable Network Based on the Star Graph. IEEE Trans. Parallel Distrib. Syst. 5(1): 97-102 (1994)

Arthur Abnous, Nader Bagherzadeh: Pipelining and Bypassing in a VLIW Processor. IEEE Trans. Parallel Distrib. Syst. 5(6): 658-664 (1994)

Steven Wallace, Nader Bagherzadeh: Performance Issues of a Superscalar Microprocessor. ICPP (1) 1994: 293-297

Alireza Kavianpour, Nader Bagherzadeh: A Systematic Approch for Mapping Application Tasks in Hypercubes. IEEE Trans. Computers 42(6): 742-746 (1993)

Nader Bagherzadeh, Nayla Nassif, Shahram Latifi: A Routing and Broadcasting Scheme on Faulty Star Graphs. IEEE Trans. Computers 42(11): 1398-1403 (1993)

Shahram Latifi, Marcelo M. de Azevedo, Nader Bagherzadeh: The Star Connected Cycles: A Fixed-Degree Network for Parallel Processing. ICPP 1993: 91-95

John Lenell, Nader Bagherzadeh: A Performance Comparison of Several Superscalar Processor Models with a VLIW Processor. IPPS 1993: 44-48

Shahram Latifi, Nader Bagherzadeh: The Clustered-Star Graph: A New Topology for Large Interconnection Networks. IPPS 1993: 514-518

Alireza Kavianpour, Nader Bagherzadeh: Finding circular shapes in an image on a pyramid architecture. Pattern Recognition Letters 13(12): 843-848 (1992)

Shahram Latifi, Si-Qing Zheng, Nader Bagherzadeh: Optimal Ring Embedding in Hypercubes with Faulty Links. FTCS 1992: 178-184

Takaaki Kato, Koji Suginuma, Nader Bagherzadeh: On Design and Performance Analysis of a Superscalar Architecture. ICPP (1) 1992: 171-178

Nader Bagherzadeh, Kent Hawk: Parallel Implementation of the Auction Algorithm on the Intel Hypercube. IPPS 1992: 443-447

Takaaki Kato, Toshihisa Ono, Nader Bagherzadeh: Performance analysis and design methodology for a scalable superscalar architecture. MICRO 1992: 246-255

Nader Bagherzadeh, Seng-lai Heng, Chuan-lin Wu: A Parallel Asynchronous Garbage Collection Algorithm for Distributed Systems. IEEE Trans. Knowl. Data Eng. 3(1): 100-107 (1991)

Arthur Abnous, Roni Potasman, Nader Bagherzadeh, Alexandru Nicolau: A Percolation Based VLIW Architecture. ICPP (1) 1991: 144-148

Alireza Kavianpour, Nader Bagherzadeh: Parallel Hough Transform for Image Processing on a Pyramid Architecture. ICPP (1) 1991: 395-398

Wei-Kang Tsai, Nader Bagherzadeh, Young C. Kim: Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing. ICPP (1) 1991: 696-697

Arthur Abnous, Nader Bagherzadeh: Special Features of a VLIW Architecture. IPPS 1991: 224-227

Douglas M. Blough, Nader Bagherzadeh: Near-optimal message routing and broadcasting in faulty hypercubes. International Journal of Parallel Programming 19(5): 405-423 (1990)

Adolfo Guzmán, Edward J. Krall, Patrick F. McGehearty, Nader Bagherzadeh: Performance of symbolic applications on a parallel architecture. International Journal of Parallel Programming 16(3): 183-214 (1987)

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