M. Balakrishnan

B. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan: Accelerating 3D-FFT Using Hard Embedded Blocks in FPGAs. VLSI Design 2013: 92-97

G. Marimuthu, M. Balakrishnan: E-super vertex magic labelings of graphs. Discrete Applied Mathematics 160(12): 1766-1774 (2012)

Sonali Chouhan, M. Balakrishnan, Ranjan Bose: System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation. IEEE Trans. on CAD of Integrated Circuits and Systems 31(4): 586-596 (2012)

M. Balakrishnan, Hong Huang, Rafael Asorey-Cacheda, Satyajayant Misra, Sandeep Pawar, Yousef Jaradat: Measures and Countermeasures for Null Frequency Jamming of On-Demand Routing Protocols in Wireless Ad Hoc Networks. IEEE Transactions on Wireless Communications 11(11): 3860-3868 (2012)

M. Balakrishnan: Power Consumption in Multi-core Processors. IC3 2012: 3

Arun Parakh, M. Balakrishnan, Kolin Paul: Performance Estimation of GPUs with Cache. IPDPS Workshops 2012: 2384-2393

Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata. JETC 7(3): 13 (2011)

Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi: Compressing Cache State for Postsilicon Processor Debug. IEEE Trans. Computers 60(4): 484-497 (2011)

Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: Architecture and tools for programmable QCA. FPT 2011: 1-4

Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: A tiled programmable fabric using QCA. FPT 2010: 9-16

Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan: Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC 2010: 55-60

Rajeswari Devadoss, Kolin Paul, M. Balakrishnan: Clocking-Based Coplanar Wire Crossing Scheme for QCA. VLSI Design 2010: 339-344

Sonali Chouhan, Ranjan Bose, M. Balakrishnan: A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1017-1024 (2009)

Sonali Chouhan, Ranjan Bose, M. Balakrishnan: Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes. IEEE Transactions on Wireless Communications 8(10): 5348-5355 (2009)

Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan: Online cache state dumping for processor debug. DAC 2009: 358-363

Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan: Cache aware compression for processor debug support. DATE 2009: 208-213

Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda: A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors. DATE 2009: 1018-1023

Sonali Chouhan, M. Balakrishnan, Ranjan Bose: An experimental validation of system level design space exploration methodology for energy efficient sensor nodes. ISLPED 2009: 355-358

Sonali Chouhan, M. Balakrishnan, Ranjan Bose: A framework for energy consumption based design space exploration for wireless sensor nodes. ISLPED 2008: 329-334

Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. International Journal of Parallel Programming 35(6): 507-527 (2007)

Anup Gangwar, M. Balakrishnan, Anshul Kumar: Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. ACM Trans. Design Autom. Electr. Syst. 12(1) (2007)

Ashutosh Pal, M. Balakrishnan: A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures. FPL 2007: 517-520

M. Balakrishnan, N. Ravisankar, K. Meena, R. Elanchezhian, S. K. Zamir Ahmed: Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands. IICAI 2007: 1533-1541

Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan: New approach to architectural synthesis: incorporating QoS constraint. EMSOFT 2006: 301-310

Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar: Rapid Resource-Constrained Hardware Performance Estimation. IEEE International Workshop on Rapid System Prototyping 2006: 40-46

Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra: Sequential Equivalence Checking. VLSI Design 2006: 18-19

Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar: Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. DATE 2005: 730-735

Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee: SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only). FPGA 2005: 273

M. Balakrishnan, B. S. Panwar: A Specialized Graduate Program in VLSI Design Tools and Technology. MSE 2005: 83-84

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: Integrated On-Chip Storage Evaluation in ASIP Synthesis. VLSI Design 2005: 274-279

Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan: ADOPT: An Approach to Activity Based Delay Optimization. VLSI Design 2005: 411-416

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: An efficient technique for exploring register file size in ASIP design. IEEE Trans. on CAD of Integrated Circuits and Systems 23(12): 1693-1699 (2004)

Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Automatic synthesis of system on chip multiprocessor architectures for process networks. CODES+ISSS 2004: 60-65

Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Synthesis of Application Specific Multiprocessor Architectures for Process Networks. VLSI Design 2004: 780-783

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: Exploring Storage Organization in ASIP Synthesis. DSD 2003: 120-127

Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar: SoC Synthesis with Automatic Hardware Software Interface Generation. VLSI Design 2003: 585-

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: An efficient technique for exploring register file size in ASIP synthesis. CASES 2002: 252-261

Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel: Scratchpad memory: design alternative for cache on-chip memory in embedded systems. CODES 2002: 73-78

M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha: A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units. ISSS 2002: 2-7

M. Balakrishnan, Anshul Kumar, C. P. Joshi: A New Performance Evaluation Approach for System Level Design Space Exploration. ISSS 2002: 180-185

M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke: Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory. ISSS 2002: 213-218

Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar: Exploring the Number of Register Windows in ASIP Synthesis. VLSI Design 2002: 233-238

Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan: A New Divide and Conquer Method for Achieving High Speed Division in Hardware. VLSI Design 2002: 535-540

Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan: Analysis of the influence of register file size on energyconsumption, code size, and execution time. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1329-1337 (2001)

Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan: Exploring design space of parallel realizations: MPEG-2 decoder case study. CODES 2001: 92-97

Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan: Evaluating register file size in ASIP design. CODES 2001: 109-114

M. Balakrishnan: A Specialized Graduate Program in VLSI Design: A Success Story. MSE 2001: 85-86

Anupam Rastogi, M. Balakrishnan, Anshul Kumar: Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. VLSI Design 2001: 23-28

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar: ASIP Design Methodologies : Survey and Issues. VLSI Design 2001: 76-

M. Balakrishnan, Heman Khanna: Allocation of FIFO structures in RTL data paths. ACM Trans. Design Autom. Electr. Syst. 5(3): 294-310 (2000)

Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan: Speeding up power estimation of embedded software. ISLPED 2000: 191-196

Arvind Rajawat, M. Balakrishnan, Anshul Kumar: nterface Synthesis: Issues and Approaches. VLSI Design 2000: 92

T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik: Processor Evaluation in an Embedded Systems Design Environment. VLSI Design 2000: 98-103

Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan: Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming. VLSI Design 2000: 110-113

M. Anand, Sanjiv Kapoor, M. Balakrishnan: Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware. FPGA 1999: 249

Rashmi Goswami, V. Srinivasan, M. Balakrishnan: MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign. VLSI Design 1999: 128-132

Ajoy C. Siddabathuni, M. Balakrishnan: Simulation and Modeling of a Multicast ATM Switch. VLSI Design 1999: 242-

A. R. Naseer, M. Balakrishnan, Anshul Kumar: Direct mapping of RTL structures onto LUT-based FPGA's. IEEE Trans. on CAD of Integrated Circuits and Systems 17(7): 624-631 (1998)

Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee: Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign. VLSI Design 1998: 97-

Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar: Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library. VLSI Design 1998: 400-405

M. Balakrishnan, R. Cohen: Global Optimization of Multiplexed Video Encoders. ICIP (1) 1997: 377-380

Heman Khanna, M. Balakrishnan: Allocation of FIFO Structures in RTL Data Paths. VLSI Design 1997: 130-133

A. R. Naseer, M. Balakrishnan, Anshul Kumar: Optimal Clock Period for Synthesized Data Paths. VLSI Design 1997: 134-139

Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar: A Novel Reconfigurable Co-Processor Architecture. VLSI Design 1997: 370-375

A. R. Naseer, M. Balakrishnan, Anshul Kumar: Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs. FPL 1995: 139-148

M. Balakrishnan: Buffer constraints in a variable-rate packetized video system. ICIP 1995: 29-32

Alok Kumar, Anshul Kumar, M. Balakrishnan: Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis. VLSI Design 1995: 75-80

A. R. Naseer, M. Balakrishnan, Anshul Kumar: An Efficient Technique for Mapping RTL Structures onto FPGAs. FPL 1994: 99-110

Atul Varshneya, B. B. Madan, M. Balakrishnan: Concurrent Search and Insertion in K-Dimensional Height Balanced Trees. IPPS 1994: 883-887

A. R. Naseer, M. Balakrishnan, Anshul Kumar: FAST: FPGA Targeted RTL Structure Synthesis Technique. VLSI Design 1994: 21-24

C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer: High Level Design Experiences with IDEAS. VLSI Design 1993: 110

M. V. Rao, M. Balakrishnan, Anshul Kumar: DESSERT: Design Space Exploration of RT Level Components. VLSI Design 1993: 299-304

M. Balakrishnan, Peter Marwedel: Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration. DAC 1989: 68-74

M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders: A Semantic Approach for Modular Synthesis of VLSI Systems. Inf. Process. Lett. 27(1): 1-7 (1988)

M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia: Allocation of multiport memories in data path synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 536-540 (1988)