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 | 2008 | |
|---|---|---|
| j2 |      | Armando Mora Campos, Francisco Ballester, Marcos Martínez Peiró, José A. Canals Esteve: Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management. Microprocessors and Microsystems - Embedded Hardware Design 32(2): 68-78 (2008) |
| 2004 | ||
| j1 | | Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco Ballester, Marcos Martínez Peiró: Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices. Microprocessors and Microsystems 28(9): 509-518 (2004) |
| c5 | | Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer: FPGA Custom DSP for ECG Signal Analysis and Compression. FPL 2004: 954-958 |
| c4 | | Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá: Architectures for ICT on FPGA. FPT 2004: 403-406 |
| c3 |  | Arturo Méndez Patiño, Marcos Martínez Peiró, Francisco Ballester, Guillermo Payá Vayá: 2D-DCT on FPGA by polynomial transformation in two-dimensions. ISCAS (3) 2004: 365-368 |
| 2003 | ||
| c2 | | Guillermo Payá Vayá, Marcos Martínez Peiró, Francisco Ballester, Francisco Mora Campos: Fully Parameterized Discrete Wavelet Packet Transform Architecture Oriented to FPGA. FPL 2003: 533-542 |
| 2000 | ||
| c1 | | Rafael Gadea Gironés, Joaquín Cerdá, Francisco Ballester, Antonio Mocholí Salcedo: Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation. ISSS 2000: 225-230 |
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