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Yongchan Ban
2010 – today
- 2012
[c8]Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan: Dealing with IC manufacturability in extreme scaling (Embedded tutorial paper). ICCAD 2012: 240-242- 2011
- [j2]Yongchan Ban, David Z. Pan: Modeling of Layout Aware Line-Edge Roughness and Poly Optimization for Leakage Minimization. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 150-159 (2011)
- [c7]Yongchan Ban, Jae-Seok Yang: Layout aware line-edge roughness modeling and poly optimization for leakage minimization. DAC 2011: 447-452
- [c6]Yongchan Ban, Kevin Lucas, David Z. Pan: Flexible 2D layout decomposition framework for spacer-type double pattering lithography. DAC 2011: 789-794
- [c5]Yen-Hung Lin, Yongchan Ban, David Z. Pan, Yih-Lang Li: Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing. ICCAD 2011: 283-289
- 2010
- [c4]Yongchan Ban, David Z. Pan: Compact modeling and robust layout optimization for contacts in deep sub-wavelength lithography. DAC 2010: 408-411
- [c3]Yongchan Ban, Savithri Sundareswaran, David Z. Pan: Total sensitivity based dfm optimization of standard library cells. ISPD 2010: 113-120
2000 – 2009
- 2009
- [j1]Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan: ELIAD: Efficient Lithography Aware Detailed Routing Algorithm With Compact and Macro Post-OPC Printability Prediction. IEEE Trans. on CAD of Integrated Circuits and Systems 28(7): 1006-1016 (2009)
- 2008
- [c2]Minsik Cho, Kun Yuan, Yongchan Ban, David Z. Pan: ELIAD: efficient lithography aware detailed router with compact post-OPC printability prediction. DAC 2008: 504-509
- [c1]Minsik Cho, Yongchan Ban, David Z. Pan: Double patterning technology friendly detailed routing. ICCAD 2008: 506-511
Coauthor Index
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last updated on 2013-03-12 21:28 CET by the dblp team