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Savita Banerjee
2010 – today
- 2010
[c8]Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty: Layout-aware Illinois Scan design for high fault coverage coverage. ISQED 2010: 683-688- [c7]Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir: On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291
2000 – 2009
- 2006
- [c6]B. Mazumdar, A. Mediratta, J. Bhattacharyya, Savita Banerjee: A Real Time Speckle Noise Cleaning Filter for Ultrasound Images. CBMS 2006: 341-346
- 2000
- [j3]Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan: Buffer Assignment Algorithms on Data Driven ASICs. IEEE Trans. Computers 49(1): 16-32 (2000)
1990 – 1999
- 1996
- [j2]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar: Initialization issues in asynchronous circuit synthesis. J. Electronic Testing 9(3): 237-250 (1996)
- [j1]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of initializable asynchronous circuits. IEEE Trans. VLSI Syst. 4(2): 254-263 (1996)
- [c5]Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy: Synchronous Test Generation Model for Asynchronous Circuits. VLSI Design 1996: 178-185
- 1994
- [c4]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Signal Transition Graph Transformations for Initializability. EDAC-ETC-EUROASIC 1994: 670
- [c3]Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan: Initialization Isuues in the Synthesis of Asynchronous Circuits. ICCD 1994: 447-452
- [c2]Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan: Synthesis of Initializable Asynchronous Circuits. VLSI Design 1994: 383-388
- 1993
- [c1]Dhiraj K. Pradhan, Mitrajit Chatterjee, Savita Banerjee: Buffer assignment for data driven architectures. ICCAD 1993: 665-668
Coauthor Index
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last updated on 2012-12-02 21:27 CET by the dblp team