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 | 2013 | |
|---|---|---|
| c34 |      | Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari: Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs. ARCS 2013: 134-146 |
| c33 | | |
| 2012 | ||
| j10 | | Saman Khoshbakht, Amirali Baniasadi: Leakage-Aware Speculative Branch Target Buffer. J. Low Power Electronics 8(5): 595-603 (2012) |
| j9 | | Narges Shahidi, Ali Shafiee, Amirali Baniasadi: Heterogeneous Interconnect for Low-Power Snoop-Based Chip Multiprocessors. J. Low Power Electronics 8(5): 624-635 (2012) |
| c32 | | Ali Jooya, Amirali Baniasadi, Nikitas J. Dimopoulos: Efficient Design Space Exploration of GPGPU Architectures. Euro-Par Workshops 2012: 518-527 |
| c31 | | Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari: Dynamic warp resizing: Analysis and benefits in high-performance SIMT. ICCD 2012: 502-503 |
| i2 | | Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari: Investigating Warp Size Impact in GPUs. CoRR abs/1205.4967 (2012) |
| i1 | | Ahmad Lashgar, Amirali Baniasadi, Ahmad Khonsari: Dynamic Warp Resizing in High-Performance SIMT. CoRR abs/1208.2374 (2012) |
| 2011 | ||
| c30 | | Mohsen Taherian, Amirali Baniasadi, Hamid Noori: Instruction and data cache peak temperature reduction using cache access balancing in embedded processors. AICCSA 2011: 285-286 |
| c29 | | Farzad Samie, Amirali Baniasadi: Power and frequency analysis for data and control independence in embedded processors. IGCC 2011: 1-6 |
| c28 | | Mostafa Kishani, Amirali Baniasadi, Hossein Pedram: Using Silent Writes in Low-Power Traffic-Aware ECC. PATMOS 2011: 180-192 |
| 2010 | ||
| j8 | | Kaveh Jokar Deris, Amirali Baniasadi: Power-aware BTB for modern processors. Computers & Electrical Engineering 36(5): 902-911 (2010) |
| c27 | | |
| c26 | | Ali Shafiee, Narges Shahidi, Amirali Baniasadi: Helia: Heterogeneous Interconnect for Low Resolution Cache Access in snoop-based chip multiprocessors. ICCD 2010: 84-91 |
| c25 | | Ali Shafiee, Narges Shahidi, Amirali Baniasadi: Using Partial Tag Comparison in Low-Power Snoop-Based Chip Multiprocessors. ISCA Workshops 2010: 211-221 |
| c24 | | Alireza Haghdoost, Hossein Asadi, Amirali Baniasadi: System-Level Vulnerability Estimation for Data Caches. PRDC 2010: 157-164 |
| 2009 | ||
| j7 | | Tooraj Nikoubin, Fatemeh Eslami, Amirali Baniasadi, Keivan Navi: A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic. J. Low Power Electronics 5(4): 474-483 (2009) |
| j6 | | Amirali Baniasadi, Babak Salamat, Kaveh Jokar Deris: Power-aware scoreboard alternatives for multimedia processors. Microprocessors and Microsystems - Embedded Hardware Design 33(4): 326-332 (2009) |
| c23 | | Fatemeh Eslami, Amirali Baniasadi, Mostafa Farahani: Application Specific Transistor Sizing for Low Power Full Adders. ASAP 2009: 195-198 |
| c22 | | Newsha Ardalani, Amirali Baniasadi: Write Invalidation Analysis in Chip Multiprocessors. PATMOS 2009: 196-205 |
| 2008 | ||
| j5 | | Ehsan Atoofian, Amirali Baniasadi: Using supplier locality in power-aware interconnects and caches in chip multiprocessors. Journal of Systems Architecture - Embedded Systems Design 54(5): 507-518 (2008) |
| c21 | | Ehsan Atoofian, Amirali Baniasadi, Yvonne Coady: Adaptive Read Validation in Time-Based Software Transactional Memory. Euro-Par Workshops 2008: 152-162 |
| c20 | | Ehsan Atoofian, Amirali Baniasadi: Exploiting program cyclic behavior to reduce memory latency in embedded processors. SAC 2008: 1482-1486 |
| 2007 | ||
| j4 | | Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai: Exploiting Speculation Cost Prediction in Power-Aware Applications. J. Low Power Electronics 3(1): 43-53 (2007) |
| j3 | | Ehsan Atoofian, Amirali Baniasadi: Speculative trivialization point advancing in high-performance processors. Journal of Systems Architecture 53(9): 587-601 (2007) |
| j2 | | Kaveh Jokar Deris, Amirali Baniasadi: Investigating cache energy and latency break-even points in high performance processors. SIGARCH Computer Architecture News 35(4): 13-20 (2007) |
| c19 | | Daniel C. Vanderster, Amirali Baniasadi, Nikitas J. Dimopoulos: Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for Computational Clusters. Asia-Pacific Computer Systems Architecture Conference 2007: 175-185 |
| c18 | | Kaveh Aasaraai, Amirali Baniasadi: A Power-Aware Alternative for the Perceptron Branch Predictor. Asia-Pacific Computer Systems Architecture Conference 2007: 198-208 |
| c17 | | Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian: Computational and storage power optimizations for the O-GEHL branch predictor. Conf. Computing Frontiers 2007: 105-112 |
| c16 | | Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai: Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. Conf. Computing Frontiers 2007: 259-266 |
| c15 | | Ehsan Atoofian, Amirali Baniasadi: A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors. IPDPS 2007: 1-8 |
| 2006 | ||
| j1 | | Kaveh Aasaraai, Amirali Baniasadi: Low-Power Perceptron Branch Predictor. J. Low Power Electronics 2(3): 333-341 (2006) |
| c14 | | Kaveh Jokar Deris, Amirali Baniasadi: Branchless cycle prediction for embedded processors. SAC 2006: 928-932 |
| c13 | | Babak Salamat, Amirali Baniasadi, Kaveh Jokar Deris: Area-Aware Optimizations for Resource Contrained Branch Predictors Exploited in Embedded Processors. ICSAMOS 2006: 50-55 |
| c12 | | Houman Homayoun, Amirali Baniasadi: Reducing Execution Unit Leakage Power in Embedded Processors. SAMOS 2006: 299-308 |
| 2005 | ||
| c11 | | Amirali Baniasadi: Balancing clustering-induced stalls to improve performance in clustered processors. Conf. Computing Frontiers 2005: 21-27 |
| c10 | | Ehsan Atoofian, Amirali Baniasadi: Improving Energy-Efficiency by Bypassing Trivial Computations. IPDPS 2005 |
| c9 | | Babak Salamat, Amirali Baniasadi: Area-Aware Pipeline Gating for Embedded Processors. PATMOS 2005: 601-608 |
| 2004 | ||
| c8 | | Amirali Baniasadi, Andreas Moshovos: SEPAS: a highly accurate energy-efficient branch predictor. ISLPED 2004: 38-43 |
| 2003 | ||
| c7 | | Amirali Baniasadi: Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures. DSD 2003: 240-247 |
| c6 | | Amirali Baniasadi: Power-Aware Branch Predictor Update for High-Performance Processors. PATMOS 2003: 420-429 |
| 2002 | ||
| c5 | | Amirali Baniasadi, Andreas Moshovos: Branch Predictor Prediction: A Power-Aware Branch Predictor for High-Performance Processors. ICCD 2002: 458-461 |
| c4 | | Amirali Baniasadi, Andreas Moshovos: Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. ISLPED 2002: 255-258 |
| 2001 | ||
| c3 | | Andreas Moshovos, Dionisios N. Pnevmatikatos, Amirali Baniasadi: Slice-processors: an implementation of operation-based prediction. ICS 2001: 321-334 |
| c2 | | Amirali Baniasadi, Andreas Moshovos: Instruction flow-based front-end throttling for power-aware high-performance processors. ISLPED 2001: 16-21 |
| 2000 | ||
| c1 | | Amirali Baniasadi, Andreas Moshovos: Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors. MICRO 2000: 337-347 |
Colors in the list of coauthors
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